Omega Engineering PCI-DAS1200 manual ADC Channel MUX and Control Register

EOBI	Status bit ADC End-of-Burst interrupt. Only valid for ADC Burst Mode enabled.
	1	= Indicates an	EOB interrupt has been latched.
	0	= Indicates an	EOB interrupt has not occurred.
ADHFI	Status bit of ADC FIFO Half-Full interrupt. Used during REP INSW operations.
	1	= Indicates an ADC Half-Full interrupt has been latched. FIFO has been filled
		with more than 255 samples.
	0	= Indicates an ADC Half-Full interrupt has not occurred. FIFO has not yet
		exceeded 1/2 of its total capacity.
ADNEI	Status bit of ADC FIFO Not-Empty interrupt. Used to indicate ADC conversion
	complete in single conversion applications.
	1	= Indicates an ADC FIFO Not-Empty interrupt has been latched and that
		one data word may be read from the FIFO.
	0	= Indicates an ADC FIFO Not-Empty interrupt has not occurred. FIFO has
		been cleared, read until empty or ADC conversion still in progress.
ADNE	Real-time status bit of ADC FIFO Not-Empty status signal.
	1	= Indicates ADC FIFO has at least one word to be read.
	0	= Indicates ADC FIFO is empty.
LADFUL	Status bit of ADC FIFO FULL status. This bit is latched.
	1	= Indicates the ADC FIFO has exceeded full state. Data may have been lost.
	0	= Indicates non-overflow condition of ADC FIFO.

7.3.2 ADC CHANNEL MUX AND CONTROL REGISTER

BADR1 + 2

This register sets channel mux HI/LO limits, ADC gain, offset and pacer source.

A Read/Write register.

WRITE

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
-	-	ADPS1	ADPS0	UNIBIP	SEDIFF	GS1	GS0	CHH8	CHH4	CHH2	CHH1	CHL8	CHL4	CHL2	CHL1

CHL8-CHL1, CHH8-CHH1

When these bits are written, the analog input multiplexors are set to the channel specified by CHL8-CHL1. After each conversion, the input multiplexors increment to the next channel, reloading to the "CHL" start channel after the "CHH" stop channel is reached. LO and HI channels are the decode of the 4-bit binary patterns.

GS[1:0] These bits determine the ADC range as indicated below.

GS1	GS0	Range
0	0	10V
0	1	5V
1	0	2.5V
1	1	1.25V

SEDIFF Selects measurement configuration for the Analog Front-End.

1 = Analog Front-End in Single-Ended Mode. This mode supports

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