Omega Engineering PCI-DAS1200 manual ORFN$LDJUDP6-5

Page 5

Gain and Offset Autocal

Burst/Scan

Mux

&

Gain

Analog In

16CH S.E.

8CH DIFF.

Gains = 1, 2, 4, 8

	ADC
	Pacer
	CTR 2	r o l
	CTR 1	n t
	CTR 1	Co
		Co
	Sample
	Counter
	CTR0

12-Bit, 330KHz

Start EOC

EXT PCR

10 MHz

1024 x 12

FIFO

I N T

Burst/Scan

CONTROLLER

FPGA

INT

Scan

ADC

&

Pacer

Burst

Control

Logic

XTRIG Trigger

Control

Decode/Status Int		INT
		INT

Ctl

Bus

Time Base

CLK2

GATE2

OUT2

CLK1

GATE1

OUT1

INT

XTRIG

10MHz

CTR2
CTR1			o l
ADC			o n t r
Index			C
Index
Counter
User
CTR 0
			GATE
			GATE
			CLK
			CLK
			OUT
			OUT

Timing

3&,%ORFN'$'LDJUDP6-5

Digital I/O

PA (7:0)

Port A

l

Boot

BADR1

o

EEPROM

PCI

BADR2

PB (7:0)

Port B

t r

CONTROLLER

BADR3

n

BADR4

C o

Interrupt

PC (7:0)

Port C

PCI BUS (5V, 32-BIT, 33MHZ)

LOCAL BUS

2

Image 5

Contents Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Windows 95, 98 & NT InstallationUsing InstaCal DOS AND/OR Windows Testing the Installation Hardware Connections Connector PIN DiagramAnalog Connections Differential Input Which system do you have? System Grounds and IsolationSystems with Common Grounds Systems with Common Mode ground offset VoltagesSmall Common Mode Voltages Wiring ConfigurationsLarge Common Mode Voltages PCI-DAS1200 and signal source already have isolated groundsCommon Ground / Single-Ended Inputs Common Mode Voltage +/-10V Common Mode Voltage +/-10V / Single-Ended InputsBoard Programming Languages Programming & ApplicationsSelf-Calibration of the PCI-DAS1200 Alo g O u t BADR1 BADR0Interrupt / ADC Fifo Register Region Function OperationsEoaie InteEoacl IntclADC Channel MUX and Control Register EOC Input Range Input Gain Measurement ResolutionTrigger CONTROL/STATUS Register Pacer SourceTgen TS10ARM Fifo Mode Sample CTRC0SRC XtrigCal Source Calibration RegisterDAC Channel Cal Function Calen Dacen ModeSDI DACnR10ADC Data Register BADR2BADR2 + ADC Fifo Clear RegisterADC Pacer Clock Data and Control Registers BADR38254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3 +Base + 8254A Counter 2 Data ADC Pacer Divider UpperADC 8254 Control Register Digital I/O Data and Control RegistersDIO Control Register DIO Port B DataDIO Port C Data Counter DATA-ADC Index and User Counter Data and Control Registers 8254BPRE-TRIGGER Index Counter Or User8254B Counter 2 Data User Counter #6 8254B Counter 1 Data User Counter #5BADR3 + Ah 8254B Control Register2 DAC1 Data Register BADR41 DAC0 Data Register Analog Input Section Electrical SpecificationsParallel Digital Input / Output Analog Output82C54A Counter SectionEnvironmental Other SpecificationsPower consumption For Your Notes EC Declaration of Conformity