Omega Engineering PCI-DAS1200 manual ORFN3&,$LDJUDP6

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1.0 INTRODUCTION

The PCI-DAS1200 and PCI-DAS1200/JR are multifunction measurement and control boards designed to operate in computers with PCI bus accessory slots. The difference between the boards is that the analog ouput functions are not supported by the /JR board. The architecture of the boards is loosely based on the original CIO-DAS16; the standard of ISA bus data acquisition. Much has changed though, and all of it due to improvements in technology. Surface mount packaging technology and custom ASICS allow a far greater range of control over programmable options, such as calibration, triggering, synchronization, and data transfer.

Even the connector has changed. New, denser connectors allow up to 100 signal lines where 37 was once the standard.

The PCI-DAS1200 and PCI-DAS1200/JR are completely plug-and-play. There are no switches or jumpers on the board. All board addresses are set by your computer’s plug-and-play software.

These products are supported by our Universal Library programming library. As an owner, you are entitled to the latest revision of the manual and software. Just call with your current revision numbers handy, and request an update be sent to you.

Gain and Offset Autocal

Gain and Offset Autocal

Burst/Scan

Mux

&

Gain

Analog In

16CH S.E.

8CH DIFF.

Gains = 1, 2, 4, 8

	ADC
	Pacer
	CTR 2	r o l
	CTR 1	n t
	CTR 1	Co
		Co
	Sample
	Counter
	CTR0

12-Bit, 330KHz

Start EOC

EXT PCR

10 MHz

1024 x 12

FIFO

I N T

Burst/Scan

CONTROLLER

FPGA


			12-Bit, 10uS				VDAC 0
DAC			DAC0
			DAC0

Data
Control			12-Bit, 10uS				VDAC 1
			12-Bit, 10uS				VDAC 1
			DAC1
			DAC1

INT

Scan

ADC & DAC

ControlPacer BurstLogic Control

XTRIG Trigger

Control

Decode/Status Int		INT
		INT

Ctl

Bus

Time Base

CLK2

GATE2

OUT2

CLK1

GATE1

OUT1

INT

XTRIG

10MHz

CTR2
CTR1			o l
ADC			o n t r
Index			C
Index
Counter
User
CTR 0
			GATE
			GATE
			CLK
			CLK
			OUT
			OUT

Timing

%ORFN3&,'$'LDJUDP6

Digital I/O

PA (7:0)

Port A

l

Boot

BADR1

o

EEPROM

PCI

BADR2

PB (7:0)

Port B

t r

CONTROLLER

BADR3

n

BADR4

o

C

Interrupt

PC (7:0)

Port C

LOCAL BUS

PCI BUS (5V, 32-BIT, 33MHZ)

1

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Contents Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Installation Windows 95, 98 & NTUsing InstaCal DOS AND/OR Windows Testing the Installation Connector PIN Diagram Hardware ConnectionsAnalog Connections Differential Input System Grounds and Isolation Which system do you have?Systems with Common Mode ground offset Voltages Systems with Common GroundsWiring Configurations Small Common Mode VoltagesLarge Common Mode Voltages PCI-DAS1200 and signal source already have isolated grounds Common Ground / Single-Ended InputsCommon Mode Voltage +/-10V / Single-Ended Inputs Common Mode Voltage +/-10VBoard Programming & Applications Programming LanguagesSelf-Calibration of the PCI-DAS1200 Alo g O u t BADR0 BADR1Interrupt / ADC Fifo Register Region Function OperationsInte EoaieEoacl IntclADC Channel MUX and Control Register Input Range Input Gain Measurement Resolution EOCTrigger CONTROL/STATUS Register Pacer SourceTS10 TgenFifo Mode Sample CTR ARMC0SRC XtrigDAC Channel Cal Function Calibration RegisterCal Source Dacen Mode CalenSDI DACnR10BADR2 ADC Data RegisterBADR2 + ADC Fifo Clear RegisterBADR3 ADC Pacer Clock Data and Control Registers8254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3 +8254A Counter 2 Data ADC Pacer Divider Upper Base +ADC 8254 Control Register Digital I/O Data and Control RegistersDIO Port C Data DIO Port B DataDIO Control Register Index and User Counter Data and Control Registers 8254B Counter DATA-ADCPRE-TRIGGER Index Counter Or User8254B Counter 1 Data User Counter #5 8254B Counter 2 Data User Counter #6BADR3 + Ah 8254B Control Register1 DAC0 Data Register BADR42 DAC1 Data Register Electrical Specifications Analog Input SectionAnalog Output Parallel Digital Input / OutputCounter Section 82C54APower consumption Other SpecificationsEnvironmental For Your Notes EC Declaration of Conformity