Omega Engineering PCI-DAS1200 manual Calibration Register, DAC Channel Cal Function, Cal Source

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7.3.4 CALIBRATION REGISTER

As mentioned before, direct register level programming should be attempted only by extremely experienced register level programmers. This is true for register-level calibration. If you’re not sure, don’t attempt it. Call Technical Support for more information.

BADR1 + 6

This register controls all autocal operations. This is a Write-only register.

WRITE

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

SDI	CALEN	CSRC2	CSRC1	CSRC0	-	SEL7376	SEL8800	-	-	-	-	-	-	-	-

SEL8800 This bit enables the 8-bit trim DACs for the following circuits:

DAC Channel	Cal Function

0	DAC0 Fine Gain

1	DAC0 Coarse Gain

2	DAC0 Offset

3	DAC1 Offset

4	DAC1 Fine Gain

5	DAC1 Coarse Gain

6	ADC Coarse Offset

7	ADC Fine Offset

SEL7376 This bit latches the 7-bit serial data stream into the AD7376 digital potentiometer (10KOhm). The AD7376 is used for analog front-end gain calibration.

CSRC[2:0] These bits select the different calibration sources available to the ADC front end.

CSRC2	CSRC1	CSRC0	Cal Source

0	0	0	AGND

0	0	1	7.0V

0	1	0	3.5V

0	1	1	1.75V

1	0	0	0.875V

1	0	1	8.6mV

1	1	0	VDAC0

1	1	1	VDAC1

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Contents Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Installation Windows 95, 98 & NTUsing InstaCal DOS AND/OR Windows Testing the Installation Connector PIN Diagram Hardware ConnectionsAnalog Connections Differential Input System Grounds and Isolation Which system do you have?Systems with Common Mode ground offset Voltages Systems with Common GroundsWiring Configurations Small Common Mode VoltagesLarge Common Mode Voltages PCI-DAS1200 and signal source already have isolated grounds Common Ground / Single-Ended InputsCommon Mode Voltage +/-10V / Single-Ended Inputs Common Mode Voltage +/-10VBoard Programming & Applications Programming LanguagesSelf-Calibration of the PCI-DAS1200 Alo g O u t BADR0 BADR1Interrupt / ADC Fifo Register Region Function OperationsInte EoaieEoacl IntclADC Channel MUX and Control Register Input Range Input Gain Measurement Resolution EOCTrigger CONTROL/STATUS Register Pacer SourceTS10 TgenFifo Mode Sample CTR ARMC0SRC XtrigDAC Channel Cal Function Calibration RegisterCal Source Dacen Mode CalenSDI DACnR10BADR2 ADC Data RegisterBADR2 + ADC Fifo Clear RegisterBADR3 ADC Pacer Clock Data and Control Registers8254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3 +8254A Counter 2 Data ADC Pacer Divider Upper Base +ADC 8254 Control Register Digital I/O Data and Control RegistersDIO Port C Data DIO Port B DataDIO Control Register Index and User Counter Data and Control Registers 8254B Counter DATA-ADCPRE-TRIGGER Index Counter Or User8254B Counter 1 Data User Counter #5 8254B Counter 2 Data User Counter #6BADR3 + Ah 8254B Control Register1 DAC0 Data Register BADR42 DAC1 Data Register Electrical Specifications Analog Input SectionAnalog Output Parallel Digital Input / OutputCounter Section 82C54APower consumption Other SpecificationsEnvironmental For Your Notes EC Declaration of Conformity