Omega Engineering PCI-DAS1200 manual TS10, Tgen

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BADR1 + 4

This register provides control bits for all ADC trigger modes. A Read/Write register.

WRITE

15		14	13	12	11			10	9			8		7			6	5	4	3		2	1		0

-		-	C0SRC	FFM0		ARM		-	-			-			XTRCL		PRTRG	BURSTE	TGEN	-		-	TS1		TS0

TS[1:0]			These bits select one-of-two possible ADC Trigger Sources:

							TS1				TS0						Source

							0				0						Disabled

							0				1						SW Trigger

							1				0					External (Digital)

							1				1						Not Defined


				Note: TS[1:0] should be set to 0 while setting up Pacer source and count values.
TGEN			This bit is used to enable External Trigger function
				1 = External rising-edge Digital Trigger enabled.
				0 = External Digital Trigger has no effect.
				Note that the external trigger requires proper setting of the TS[1:0] and TGEN
				bits. Once these bits are set,									the next rising edge will start a Paced ADC conversion.
				Subsequent triggers will have no effect until external trigger flop is cleared (XTRCL).

BURSTE This bit enables 330 kHz ADC Burst mode. Start/Stop channels are selected via the CHLx, CHHx bits in ADC CTRL/STAT register at BADR1 + 2.

1 = Burst Mode enabled

0 = Burst Mode disabled

PRTRG This bit enables ADC Pre-trigger Mode. This bit works with the ARM and FFM0 bits when using Pre-trigger mode.

1= Enable Pre-trigger Mode

0= Disable Pre-trigger Mode

XTRCL A write-clear to reset the XTRIG flip-flop. 1 = Clear XTRIG status.

0 = No Effect.

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Contents Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Installation Windows 95, 98 & NTUsing InstaCal DOS AND/OR Windows Testing the Installation Connector PIN Diagram Hardware ConnectionsAnalog Connections Differential Input System Grounds and Isolation Which system do you have?Systems with Common Mode ground offset Voltages Systems with Common GroundsLarge Common Mode Voltages Wiring ConfigurationsSmall Common Mode Voltages PCI-DAS1200 and signal source already have isolated grounds Common Ground / Single-Ended InputsCommon Mode Voltage +/-10V / Single-Ended Inputs Common Mode Voltage +/-10VBoard Programming & Applications Programming LanguagesSelf-Calibration of the PCI-DAS1200 Alo g O u t Interrupt / ADC Fifo Register BADR0BADR1 Region Function OperationsEoacl InteEoaie IntclADC Channel MUX and Control Register Trigger CONTROL/STATUS Register Input Range Input Gain Measurement ResolutionEOC Pacer SourceTS10 TgenC0SRC Fifo Mode Sample CTRARM XtrigCal Source Calibration RegisterDAC Channel Cal Function SDI Dacen ModeCalen DACnR10BADR2 + BADR2ADC Data Register ADC Fifo Clear Register8254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3ADC Pacer Clock Data and Control Registers BADR3 +ADC 8254 Control Register 8254A Counter 2 Data ADC Pacer Divider UpperBase + Digital I/O Data and Control RegistersDIO Control Register DIO Port B DataDIO Port C Data PRE-TRIGGER Index Counter Index and User Counter Data and Control Registers 8254BCounter DATA-ADC Or UserBADR3 + Ah 8254B Counter 1 Data User Counter #58254B Counter 2 Data User Counter #6 8254B Control Register2 DAC1 Data Register BADR41 DAC0 Data Register Electrical Specifications Analog Input SectionAnalog Output Parallel Digital Input / OutputCounter Section 82C54AEnvironmental Other SpecificationsPower consumption For Your Notes EC Declaration of Conformity