Omega Engineering PCI-DAS1200 manual Hardware Connections, Connector PIN Diagram

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3.0HARDWARE CONNECTIONS

3.1CONNECTOR PIN DIAGRAM

The PCI-DAS1200 and PCI-DAS1200/JR employ a 100-pin I/O connector. Please make accurate notes and pay careful attention to wire connections. In a large system, a misplaced wire may create hours of work ‘fixing’ problems that do not exist. Note that pins 35, 36, 37, and 38 are for analog outputs and are therefore NC (no connec- tion) on the PCI-DAS1200/JR board. (Pin 77 is also NC on the /JR board).

A nalog G round

1

51

D igital A 0

A nalog Input C h 0 H igh

2

52

D igital A 1

A nalog Input C h 0 Low / 8 H igh

3

53

D igital A 2

A nalog Input C h 1 H igh

4

54

D igital A 3

A nalog Input C h 1 Low / 9 H igh

5

55

D igital A 4

A nalog Input C h 2 H igh

6

56

D igital A 5

A nalog Input C h 2 Low / 10 H igh

7

57

D igital A 6

A nalog Input C h 3 H igh

8

58

D igital A 7

A nalog Input C h 3 Low / 11 H igh

9

59

D igital B 0

A nalog Input C h 4 H igh

10

60

D igital B 1

A nalog Input C h 4 Low / 12 H igh

11

61

D igital B 2

A nalog Input C h 5 H igh

12

62

D igital B 3

A nalog Input C h 5 Low / 13 H igh

13

63

D igital B 4

A nalog Input C h 6H igh

14

64

D igital B 5

A nalog Input C h 6 Low / 14 H igh

15

65

D igital B 6

A nalog Input C h 7 H igh

16

66

D igital B 7

A nalog Input C h 7 Low / 15 H igh

17

67

D igital C 0

A nalog G round

18

68

D igital C 1

N C

19

69

D igital C 2

N C

20

70

D igital C 3

N C

21

71

D igital C 4

N C

22

72

D igital C 5

N C

23

73

D igital C 6

N C

24

74

D igital C 7

N C

25

75

N C

N C

26

76

N C

N C 27

77

10 M H z O U T

N C

28

78

N C

N C

29

79

N C

N C

30

80

C LK 6

N C

31

81

G ATE 6

N C

32

82

O U T 6

N C

33

83

N C

N C

34

84

N C

D /A G N D 0

35

85

C LK 5

D /A O U T 0

36

86

G ATE 5

D /A G N D 1 37

87

O U T 5

D /A O U T 1

38

88

N C

C LK 4

39

89

P C G round

G ATE 4

40

90

P C +12V

O U T 4

41

91

P C G round

A /D E xternal P acer

42

92

P C -12V

N C

43

93

N C

N C

44

94

N C

A /D E xternal Trigger

45

95

A /D Internal P acer O utput

N C

46

96

N C

N C

47

97

N C

P C + 5V

48

98

N C

N C

49

99

N C

P C G round

50

100

P C G round

P C I-D A S 1200 C onnector D iagram

3.2 CONNECTING SIGNALS TO THE PCI-DAS1200

The 100-pin connector provides a far greater signal density than the traditional 37-pin D type connector. In exchange for that density comes a far more complex cable and mating connector. The C100-FF-2 cable is a pair of 50-pin ribbon cables. At one end they are joined together with a 100-pin connector. From the 100-pin connector designed to mate with the PCI-DAS1200 connector, the two 50-pin ribbon cables diverge and are terminated at the other end with standard 50-pin header connectors. A CIO-MINI50 screw terminal board (or CIO-MINI50/DST with detachable screw terminals) is the ideal way to terminate real-world signals and route them into the PCI-DAS1200.

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Contents Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Installation Windows 95, 98 & NTUsing InstaCal DOS AND/OR Windows Testing the Installation Connector PIN Diagram Hardware ConnectionsAnalog Connections Differential Input System Grounds and Isolation Which system do you have?Systems with Common Mode ground offset Voltages Systems with Common GroundsLarge Common Mode Voltages Wiring ConfigurationsSmall Common Mode Voltages PCI-DAS1200 and signal source already have isolated grounds  Common Ground / Single-Ended InputsCommon Mode Voltage +/-10V / Single-Ended Inputs Common Mode Voltage +/-10VBoard Programming & Applications Programming LanguagesSelf-Calibration of the PCI-DAS1200 Alo g O u t Interrupt / ADC Fifo Register BADR0BADR1 Region Function OperationsEoacl InteEoaie IntclADC Channel MUX and Control Register Trigger CONTROL/STATUS Register Input Range Input Gain Measurement ResolutionEOC Pacer SourceTS10 TgenC0SRC Fifo Mode Sample CTRARM XtrigDAC Channel Cal Function Calibration RegisterCal Source SDI Dacen ModeCalen DACnR10BADR2 + BADR2ADC Data Register ADC Fifo Clear Register8254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3ADC Pacer Clock Data and Control Registers BADR3 +ADC 8254 Control Register 8254A Counter 2 Data ADC Pacer Divider UpperBase + Digital I/O Data and Control RegistersDIO Port C Data DIO Port B DataDIO Control Register PRE-TRIGGER Index Counter Index and User Counter Data and Control Registers 8254BCounter DATA-ADC Or UserBADR3 + Ah 8254B Counter 1 Data User Counter #58254B Counter 2 Data User Counter #6 8254B Control Register1 DAC0 Data Register BADR42 DAC1 Data Register Electrical Specifications Analog Input SectionAnalog Output Parallel Digital Input / OutputCounter Section 82C54APower consumption Other SpecificationsEnvironmental For Your Notes EC Declaration of Conformity