Omega Engineering PCI-DAS1200 manual Calen, Sdi, Dacen Mode, DACnR10

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CALEN	This bit is used to enable Cal Mode.
	1	= Selected Cal Source, CSRC[2:0], is fed into Analog Channel 0.
	0	= Analog Channel 0 functions as normal input.
SDI	Serial Data In. This bit is used to set serial address/data stream for the
	DAC8800 TrimDac and 7376 digital potentiometer. Used in conjunction
	with SEL8800 and SEL7376 bits.

7.3.5 DAC CONTROL/STATUS REGISTER (Does not apply to PCI-DAS1200/JR)

BADR1 + 8

This register selects the DAC gain/range and update modes. This is a Write-only register.

WRITE

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

-	-	-	-	DAC1R1	DAC1R0	DAC0R1	DAC0R0	MODE	-	-	-	-	-	DACEN	-

DACEN

MODE

DACnR[1:0]

This bit enables the Analog Out features of the board. 1 = DAC0/1 enabled.

0 = DAC0/1 disabled.

The power-on state of this bit is 0.

This bit determines the analog output mode of operation.

1 = Both DAC0 and DAC1 updated with data written to DAC0 data register. 0 = DACn updated with data written to DACn data register.

The power-on state of this bit is 0.

These bits select the independent gains/ranges for either DAC0 or DAC1. n=0 for DAC0 and n=1 for DAC1.

DACnR1	DACnR0	Range	LSB Size

0	0	Bipolar 5V	2.44mV

0	1	Bipolar 10V	4.88mV

1	0	Unipolar 5V	610uV

1	1	Unipolar 10V	1.22mV

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Contents Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Windows 95, 98 & NT InstallationUsing InstaCal DOS AND/OR Windows Testing the Installation Hardware Connections Connector PIN DiagramAnalog Connections Differential Input Which system do you have? System Grounds and IsolationSystems with Common Grounds Systems with Common Mode ground offset VoltagesSmall Common Mode Voltages Wiring ConfigurationsLarge Common Mode Voltages PCI-DAS1200 and signal source already have isolated groundsCommon Ground / Single-Ended Inputs Common Mode Voltage +/-10V Common Mode Voltage +/-10V / Single-Ended InputsBoard Programming Languages Programming & ApplicationsSelf-Calibration of the PCI-DAS1200 Alo g O u t BADR1 BADR0Interrupt / ADC Fifo Register Region Function OperationsEoaie InteEoacl IntclADC Channel MUX and Control Register EOC Input Range Input Gain Measurement ResolutionTrigger CONTROL/STATUS Register Pacer SourceTgen TS10ARM Fifo Mode Sample CTRC0SRC XtrigCal Source Calibration RegisterDAC Channel Cal Function Calen Dacen ModeSDI DACnR10ADC Data Register BADR2BADR2 + ADC Fifo Clear RegisterADC Pacer Clock Data and Control Registers BADR38254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3 +Base + 8254A Counter 2 Data ADC Pacer Divider UpperADC 8254 Control Register Digital I/O Data and Control RegistersDIO Control Register DIO Port B DataDIO Port C Data Counter DATA-ADC Index and User Counter Data and Control Registers 8254BPRE-TRIGGER Index Counter Or User8254B Counter 2 Data User Counter #6 8254B Counter 1 Data User Counter #5BADR3 + Ah 8254B Control Register2 DAC1 Data Register BADR41 DAC0 Data Register Analog Input Section Electrical SpecificationsParallel Digital Input / Output Analog Output82C54A Counter SectionEnvironmental Other SpecificationsPower consumption For Your Notes EC Declaration of Conformity