Omega Engineering PCI-DAS1200 manual Analog Output, Parallel Digital Input / Output

Page 38

ANALOG OUTPUT:

(Does not apply to PCI-DAS1200/JR)

Resolution

Number of channels

Output Ranges

D/A pacing

Data transfer

Offset error

Gain error

Differential nonlinearity

Integral nonlinearity

Monotonicity

D/A Gain drift

D/A Bipolar offset drift

D/A Unipolar offset drift

Throughput

Settling time (to .01% of 10V step) Slew Rate

Current Drive

Output short-circuit duration

Output Coupling

Amp Output Impedance

Miscellaneous

PARALLEL DIGITAL INPUT / OUTPUT

Digital Type

Configuration

Number of channels

Output High

Output Low

Input High

Input Low

Power-up / reset state

Interrupts

Interrupt enable

Interrupt sources

12bits

±10 V, ±5 V, 0 to 5 V, 0 to 10 V. Each channel independently programmable.

Software

Programmed I/O.

±600 µV max, all ranges (calibrated) ±0.02% FSR max (calibrated)

±1 LSB max ±1 LSB max 12 bits

±2 ppm/°C max ±5 ppm/°C max ±5 ppm/°C max

PC dependent 4 µs typ

7 V/µs

±5 mA min

25 mA indefinite dc

0.1 ohms max

Power up and reset, all DACs cleared to 0 volts, ±200 mV

82C55A

2 banks of 8, 2 banks of 4, programmable by bank as input or output

24 I/O

3.0volts @ -2.5mA min

0.4volts @ 2.5 mA max

2.0volts min, Vcc+0.5 volts absolute max

0.8volts max, GND-0.5 volts absolute min Input mode (high impedance)

INTA# - mapped to IRQn via PCI BIOS at boot-time Programmable

Residual counter, End-of-channel-scan, AD-FIFO-not-empty, AD-FIFO-half-full

35

Image 38

Contents Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Installation Windows 95, 98 & NTUsing InstaCal DOS AND/OR Windows Testing the Installation Connector PIN Diagram Hardware ConnectionsAnalog Connections Differential Input System Grounds and Isolation Which system do you have?Systems with Common Mode ground offset Voltages Systems with Common GroundsLarge Common Mode Voltages Wiring ConfigurationsSmall Common Mode Voltages PCI-DAS1200 and signal source already have isolated grounds Common Ground / Single-Ended InputsCommon Mode Voltage +/-10V / Single-Ended Inputs Common Mode Voltage +/-10VBoard Programming & Applications Programming LanguagesSelf-Calibration of the PCI-DAS1200 Alo g O u t Interrupt / ADC Fifo Register BADR0BADR1 Region Function OperationsEoacl InteEoaie IntclADC Channel MUX and Control Register Trigger CONTROL/STATUS Register Input Range Input Gain Measurement ResolutionEOC Pacer SourceTS10 TgenC0SRC Fifo Mode Sample CTRARM XtrigCal Source Calibration RegisterDAC Channel Cal Function SDI Dacen ModeCalen DACnR10BADR2 + BADR2ADC Data Register ADC Fifo Clear Register8254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3ADC Pacer Clock Data and Control Registers BADR3 +ADC 8254 Control Register 8254A Counter 2 Data ADC Pacer Divider UpperBase + Digital I/O Data and Control RegistersDIO Control Register DIO Port B DataDIO Port C Data PRE-TRIGGER Index Counter Index and User Counter Data and Control Registers 8254BCounter DATA-ADC Or UserBADR3 + Ah 8254B Counter 1 Data User Counter #58254B Counter 2 Data User Counter #6 8254B Control Register2 DAC1 Data Register BADR41 DAC0 Data Register Electrical Specifications Analog Input SectionAnalog Output Parallel Digital Input / OutputCounter Section 82C54AEnvironmental Other SpecificationsPower consumption For Your Notes EC Declaration of Conformity