Omega Engineering PCI-DAS1200 ADC Data Register, BADR2 +, ADC Fifo Clear Register, Msb Lsb

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7.4 BADR2

The I/O Region defined by BADR2 contains the ADC Data register and the ADC FIFO clear

register.

7.4.1 ADC DATA REGISTER

BADR2 + 0

ADC Data register.

WRITE

Writing to this register is only valid for SW initiated conversions. The ADC Pacer source must be set to 00 via the ADPS[1:0] bits. A null write to BADR2 + 0 will begin a single conversion. Conversion status may be determined in two ways. The EOC bit in BADR1 + 0 may be polled

until true or ADNEI (the AD FIFO not-empty interrupt) may be used to signal that the ADC conversion is complete and the data word is present in the FIFO.

READ

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

0	0	0	0	AD11	AD10	AD9	AD8	AD7	AD6	AD5	AD4	AD3	AD2	AD1	AD0

				MSB											LSB

AD[11:0] This register contains the current ADC data word. Data format is dependent upon offset mode:

Bipolar Mode: Offset Binary Coding

000 h = -FS

7FFh = Mid-scale (0V)

FFFh = +FS - 1LSB

Unipolar Mode: Straight Binary Coding

000 h = -FS (0V)

7FFh = Mid-scale (+FS/2)

FFFh = +FS - 1LSB

7.4.2 ADC FIFO CLEAR REGISTER

BADR2 + 2

ADC FIFO Clear register. A Write-only register. A write to this address location clears the ADC FIFO. Data is don't care. The ADC FIFO should be cleared before all new ADC operations.

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Contents Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Installation Windows 95, 98 & NTUsing InstaCal DOS AND/OR Windows Testing the Installation Connector PIN Diagram Hardware ConnectionsAnalog Connections Differential Input System Grounds and Isolation Which system do you have?Systems with Common Mode ground offset Voltages Systems with Common GroundsLarge Common Mode Voltages Wiring ConfigurationsSmall Common Mode Voltages PCI-DAS1200 and signal source already have isolated grounds Common Ground / Single-Ended InputsCommon Mode Voltage +/-10V / Single-Ended Inputs Common Mode Voltage +/-10VBoard Programming & Applications Programming LanguagesSelf-Calibration of the PCI-DAS1200 Alo g O u t Interrupt / ADC Fifo Register BADR0BADR1 Region Function OperationsEoacl InteEoaie IntclADC Channel MUX and Control Register Trigger CONTROL/STATUS Register Input Range Input Gain Measurement ResolutionEOC Pacer SourceTS10 TgenC0SRC Fifo Mode Sample CTRARM XtrigCalibration Register DAC Channel Cal FunctionCal Source SDI Dacen ModeCalen DACnR10BADR2 + BADR2ADC Data Register ADC Fifo Clear Register8254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3ADC Pacer Clock Data and Control Registers BADR3 +ADC 8254 Control Register 8254A Counter 2 Data ADC Pacer Divider UpperBase + Digital I/O Data and Control RegistersDIO Port B Data DIO Port C DataDIO Control Register PRE-TRIGGER Index Counter Index and User Counter Data and Control Registers 8254BCounter DATA-ADC Or UserBADR3 + Ah 8254B Counter 1 Data User Counter #58254B Counter 2 Data User Counter #6 8254B Control RegisterBADR4 1 DAC0 Data Register2 DAC1 Data Register Electrical Specifications Analog Input SectionAnalog Output Parallel Digital Input / OutputCounter Section 82C54AOther Specifications Power consumptionEnvironmental For Your Notes EC Declaration of Conformity