Omega Engineering PCI-DAS1200 manual Eoc, Trigger CONTROL/STATUS Register, Pacer Source

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up to 16 channels.

0 = Analog Front-End in Differential Mode. This mode supports up to 8 channels.

UNIBIP Selects offset configuration for the Analog Front-End.

1 = Analog Front-End Unipolar for selected range 0 = Analog Front-End Bipolar for selected range.

The following table summarizes all possible Offset/Range configurations:

UNIBIP	GS1	GS0	Input Range	Input Gain	Measurement
					Resolution

0	0	0	±10 V	1	4.88 mV

0	0	1	± 5 V	2	2.44 mV

0	1	0	±2.5 V	4	1.22 mV

0	1	1	±1.25V	8	610 µV

1	0	0	0-10V	1	2.44 mV

1	0	1	0-5V	2	1.22 mV

1	1	0	0-2.5V	4	610 µV

1	1	1	0-1.25V	8	305 µV

ADPS[1:0] These bits select the ADC Pacer Source. Maximum Internal/External Pacer frequency is 330 kHz.

ADPS1	ADPS0	Pacer Source

0	0	SW Convert

0	1	82C54 Counter/Timer

1	0	External Falling

1	1	External Rising

Note: For ADPS[1:0] = 00 case, SW conversions are initiated via a word write to BADR2 + 0. Data is ‘don't care.’

READ

15	14	13	12		11	10	9	8	7	6	5	4	3	2	1	0

-	EOC	-	-		-	-	-	-	-	-	-	-	-	-	-	-

EOC			Real-time, non-latched status of ADC End-of-Conversion signal.
			1	= ADC DONE
			0	= ADC BUSY

7.3.3 TRIGGER CONTROL/STATUS REGISTER

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Contents Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Windows 95, 98 & NT InstallationUsing InstaCal DOS AND/OR Windows Testing the Installation Hardware Connections Connector PIN DiagramAnalog Connections Differential Input Which system do you have? System Grounds and IsolationSystems with Common Grounds Systems with Common Mode ground offset VoltagesSmall Common Mode Voltages Wiring ConfigurationsLarge Common Mode Voltages PCI-DAS1200 and signal source already have isolated groundsCommon Ground / Single-Ended Inputs Common Mode Voltage +/-10V Common Mode Voltage +/-10V / Single-Ended InputsBoard Programming Languages Programming & ApplicationsSelf-Calibration of the PCI-DAS1200 Alo g O u t BADR1 BADR0Interrupt / ADC Fifo Register Region Function OperationsEoaie InteEoacl IntclADC Channel MUX and Control Register EOC Input Range Input Gain Measurement ResolutionTrigger CONTROL/STATUS Register Pacer SourceTgen TS10ARM Fifo Mode Sample CTRC0SRC XtrigDAC Channel Cal Function Calibration RegisterCal Source Calen Dacen ModeSDI DACnR10ADC Data Register BADR2BADR2 + ADC Fifo Clear RegisterADC Pacer Clock Data and Control Registers BADR38254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3 +Base + 8254A Counter 2 Data ADC Pacer Divider UpperADC 8254 Control Register Digital I/O Data and Control RegistersDIO Port C Data DIO Port B DataDIO Control Register Counter DATA-ADC Index and User Counter Data and Control Registers 8254BPRE-TRIGGER Index Counter Or User8254B Counter 2 Data User Counter #6 8254B Counter 1 Data User Counter #5BADR3 + Ah 8254B Control Register1 DAC0 Data Register BADR42 DAC1 Data Register Analog Input Section Electrical SpecificationsParallel Digital Input / Output Analog Output82C54A Counter SectionPower consumption Other SpecificationsEnvironmental For Your Notes EC Declaration of Conformity