Omega Engineering PCI-DAS1200 manual EC Declaration of Conformity

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EC Declaration of Conformity

PCI-DAS1200		High	speed analog I/O board for the PCI bus
PCI-DAS1200/JR		High	speed analog input board for the PCI bus
Part Number		Description

to which this declaration relates, meets the essential requirements, is in conformity with, and CE marking has been applied according to the relevant EC Directives listed below using the relevant section of the following EC standards and other normative documents:

EU EMC Directive 89/336/EEC: Essential requirements relating to electromagnetic compatibility.

EU 55022 Class B: Limits and methods of measurements of radio interference characteristics of information technology equipment.

EN 50082-1: EC generic immunity requirements.

IEC 801-2: Electrostatic discharge requirements for industrial process measurement and control equipment.

IEC 801-3: Radiated electromagnetic field requirements for industrial process measurements and control equipment.

IEC 801-4: Electrically fast transients for industrial process measurement and control equipment.

Carl Haapaoja, Director of Quality Assurance

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Contents Users Guide Table of Contents Table of Contents ORFN3&,$LDJUDP6 %ORFN$LDJUDP6-5 Installation Windows 95, 98 & NTUsing InstaCal DOS AND/OR Windows Testing the Installation Connector PIN Diagram Hardware ConnectionsAnalog Connections Differential Input System Grounds and Isolation Which system do you have?Systems with Common Mode ground offset Voltages Systems with Common GroundsLarge Common Mode Voltages Wiring ConfigurationsSmall Common Mode Voltages PCI-DAS1200 and signal source already have isolated grounds Common Ground / Single-Ended InputsCommon Mode Voltage +/-10V / Single-Ended Inputs Common Mode Voltage +/-10VBoard Programming & Applications Programming LanguagesSelf-Calibration of the PCI-DAS1200 Alo g O u t Interrupt / ADC Fifo Register BADR0BADR1 Region Function OperationsEoacl InteEoaie IntclADC Channel MUX and Control Register Trigger CONTROL/STATUS Register Input Range Input Gain Measurement ResolutionEOC Pacer SourceTS10 TgenC0SRC Fifo Mode Sample CTRARM XtrigCalibration Register DAC Channel Cal FunctionCal Source SDI Dacen ModeCalen DACnR10BADR2 + BADR2ADC Data Register ADC Fifo Clear Register8254A Counter 0 Data ADC Post Trigger Conversion Counter BADR3ADC Pacer Clock Data and Control Registers BADR3 +ADC 8254 Control Register 8254A Counter 2 Data ADC Pacer Divider UpperBase + Digital I/O Data and Control RegistersDIO Port B Data DIO Port C DataDIO Control Register PRE-TRIGGER Index Counter Index and User Counter Data and Control Registers 8254BCounter DATA-ADC Or UserBADR3 + Ah 8254B Counter 1 Data User Counter #58254B Counter 2 Data User Counter #6 8254B Control RegisterBADR4 1 DAC0 Data Register2 DAC1 Data Register Electrical Specifications Analog Input SectionAnalog Output Parallel Digital Input / OutputCounter Section 82C54AOther Specifications Power consumptionEnvironmental For Your Notes EC Declaration of Conformity