Omega 208H, DAQP-208, 308 user manual Digital input bit External gain select, high bit All

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5.2.4Digital I/O Register 5.2.4.1 Digital Output

The four digital output lines share the same pins on the interface connector as the four external channel selection bits. When using an expansion card(s), bit 5 of the control register (base + 2) should be set to “1” so that the four digital output lines will be driven by the external channel selection bits from the scan FIFO. If bit 5 of the control register is set to “0”(default after reset), then the four output lines are driven by the values in bits 0 to 3 latched during the last write operation. In other words, the digital output bits are valid only when the DAQP card is NOT in expansion mode. Table 5-14 lists the digital output register bit definition.

Table 5-14. Digital Output Register Bit Definition

 

Bits

Normal Mode

Expansion Mode

 

 

 

 

 

 

 

 

 

0-3

Digital output bits 0-3

IgnoredIgnored, the four output lines will

 

 

 

 

 

be driven by the external channel selection

 

 

 

 

bits in the scan list FIFO

 

 

 

 

 

 

 

4-7

Reserved as all “0”

Ignored

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5.2.4.2 Digital Input

Two of the digital input lines are shared with the external trigger (bit 0) and the external clock (bit 2). The other two lines are used for external gain control in expansion mode (if bit 2 of the control register is set to “1”). The digital input lines are not latched.

Although the digital input lines are also used as external trigger, external clock and the external gain selection; the current status of these lines will always be returned when reading the port. The line status does not affect the digital output register. It’s contents cannot be read back directly, even though they share the same port offset with the digital input register. Table 5-15 lists the digital input register bit definition.

Table 5-15. Digital Input Register Bit Definition

 

Bits

Normal Mode

Expansion Mode

 

 

 

 

 

 

 

 

 

0

Digital input bit 0, also serve as external trigger

The same as in normal mode

 

 

 

 

 

 

 

 

1

Digital input bit 1

External gain select, low bit

 

 

 

 

 

 

 

 

2

Digital input bit 2, also serve as external clock

The same as in normal mode

 

 

 

 

 

 

 

 

3

Digital input bit 3

External gain select, high bit

 

 

 

 

 

 

 

 

4-7

All “0”

All “0”

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DAQP-208/208H/308 Users Manual

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Contents Type II Pcmcia Data Acquisition Adapter s DAQP-208/208H/308WARRANTY/DISCLAIMER For immediate technical or application assistance Servicing North AmericaServicing Europe Page Page Table of Contents Page List of Figures and Tables Daqp Series Card Output ConnectorIntroduction Hardware Configuration and Initial Setup Page Software Installation Windows NT Page Data Acquisition Software and Drivers DAQPACL.SYS DAQPAEN.EXE Page Device = C\DAQPACL.SYS Device = C\DAQPACL.SYS b300,i5 Page Page Page Device = C\DAQPAEN.EXE S0,r GND DA0 DA1 Field WiringGND CP-DAQPA Cable AssemblyDaqp Series Card Cable Mapping UIO-37 Terminal Block UIO-37 Screw Terminal BlockTheory of Operation DC/DC Power SupplyProgrammable Gain Control Amplifier Analog Input MultiplexerScan List Register Trigger Circuit A/D Converter and Data Fifo Digital I/O Interrupt and StatusFifo A/D State Machine10 D/A Circuit Timer/CounterPage Pcmcia Interface O RegistersSreset Address Map Bit Page Data Fifo Threshold Setting LSB 1080 Select channel 0, gain 2, 1st entry Page Page Page Page Digital input bit External gain select, high bit All Output Flush scan list command High byte of the almost full threshold 15 2K option 18. D/A Data Port Bit Definition Bits Explanation 15-13 19. D/A Update Modes 20. Timer/Counter Modes Page Page Page Specifications TTL DAQP-208/208H/308 Version April 12