5.2.4Digital I/O Register 5.2.4.1 Digital Output
The four digital output lines share the same pins on the interface connector as the four external channel selection bits. When using an expansion card(s), bit 5 of the control register (base + 2) should be set to “1” so that the four digital output lines will be driven by the external channel selection bits from the scan FIFO. If bit 5 of the control register is set to “0”(default after reset), then the four output lines are driven by the values in bits 0 to 3 latched during the last write operation. In other words, the digital output bits are valid only when the DAQP card is NOT in expansion mode. Table
Table
| Bits | Normal Mode | Expansion Mode |
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| Digital output bits | IgnoredIgnored, the four output lines will |
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| be driven by the external channel selection |
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| bits in the scan list FIFO |
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| Reserved as all “0” | Ignored |
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5.2.4.2 Digital Input
Two of the digital input lines are shared with the external trigger (bit 0) and the external clock (bit 2). The other two lines are used for external gain control in expansion mode (if bit 2 of the control register is set to “1”). The digital input lines are not latched.
Although the digital input lines are also used as external trigger, external clock and the external gain selection; the current status of these lines will always be returned when reading the port. The line status does not affect the digital output register. It’s contents cannot be read back directly, even though they share the same port offset with the digital input register. Table
Table
| Bits | Normal Mode | Expansion Mode |
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| 0 | Digital input bit 0, also serve as external trigger | The same as in normal mode |
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| 1 | Digital input bit 1 | External gain select, low bit |
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| 2 | Digital input bit 2, also serve as external clock | The same as in normal mode |
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| 3 | Digital input bit 3 | External gain select, high bit |
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| All “0” | All “0” |
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49 |