Omega 308, DAQP-208, 208H user manual A/D Converter and Data Fifo

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4.6 A/D Converter and Data FIFO

The DAQP card always assumes a bipolar input range of ±10V if the gain is one. The output data format will always be in 2's complement (and left justified for 12-bit versions). The data acquisition time of the A/D converter is 2 µs while it’s conversion time is no more than 8 µs. The output of the A/D converter is fed into a data FIFO providing data buffering of up to 512 samples (2048 with 2K option installed).

The A/D converter, once triggered, will complete conversion for every analog input channel specified in the scan list at the specified scan speed and then feed the results into the data FIFO. In between scans, the DAQP card waits until another trigger is received (one-shot mode) or the pacer clock fires (continuous mode).

The data FIFO has two programmable thresholds, one for almost full and the other for almost empty. The DAQP card uses the almost full threshold and ignores the other one.

The data FIFO should always be flushed prior to using the arm/trig command to start data acquisition. When the FIFO is flushed or emptied by the host reading its content, the FIFO empty flag will be set. As long as there are samples left in the data FIFO, the empty flag will be cleared.

When the number of data samples in the FIFO becomes greater than the programmed almost full threshold, the almost full flag is set. When the number becomes less than or equal to the specified almost full threshold, the flag will be cleared. On power up or reset, the threshold is defaulted at 7 bytes to full (3.5 samples). Correct setting of the threshold will help achieve optimal performance of the card.

When the FIFO is full, the full flag will be set, and no more samples can be written into the FIFO. At the end of each scan, the DAQP card will set the data lost flag if the data FIFO is already full. This flag will not be set before or during the scan, but at the end of it. Once the data lost flag is set, it will not be cleared until the status register is read.

The data lost bit in the status register (base + 2) will be set when data continues to enter the A/D data FIFO while it is already full. With the pre-trigger option, the data lost bit is also set when an external trigger is received before the programmed data FIFO threshold is reached.

DAQP-208/208H/308 Users Manual

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Contents DAQP-208/208H/308 Type II Pcmcia Data Acquisition Adapter sWARRANTY/DISCLAIMER Servicing Europe Servicing North AmericaFor immediate technical or application assistance Page Page Table of Contents Page Daqp Series Card Output Connector List of Figures and TablesIntroduction Hardware Configuration and Initial Setup Page Software Installation Windows NT Page Data Acquisition Software and Drivers DAQPACL.SYS DAQPAEN.EXE Page Device = C\DAQPACL.SYS Device = C\DAQPACL.SYS b300,i5 Page Page Page Device = C\DAQPAEN.EXE S0,r Field Wiring GND DA0 DA1CP-DAQPA Cable Assembly GNDDaqp Series Card Cable Mapping UIO-37 Screw Terminal Block UIO-37 Terminal BlockDC/DC Power Supply Theory of OperationAnalog Input Multiplexer Programmable Gain Control AmplifierScan List Register Trigger Circuit A/D Converter and Data Fifo Interrupt and Status Digital I/OA/D State Machine FifoTimer/Counter 10 D/A CircuitPage O Registers Pcmcia InterfaceSreset Address Map Bit Page Data Fifo Threshold Setting LSB 1080 Select channel 0, gain 2, 1st entry Page Page Page Page Digital input bit External gain select, high bit All Output Flush scan list command High byte of the almost full threshold 15 2K option 18. D/A Data Port Bit Definition Bits Explanation 15-13 19. D/A Update Modes 20. Timer/Counter Modes Page Page Page Specifications TTL DAQP-208/208H/308 Version April 12