Omega 208H, DAQP-208, 308 user manual Lsb

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5.2.1.3 FIFO Flags

When reading the register under mode 1 or 3, the first available data byte from the data FIFO will be returned if it is not empty, otherwise the returned byte is not defined. The FIFO full flag will be cleared after the data FIFO register is read provided there are no more data bytes written into the FIFO by the A/D converter under mode 1 or 3. The same will happen to the FIFO almost full flag if the data bytes available in the FIFO are less than the almost full threshold. The FIFO empty flag will be set immediately after the last byte is read from the FIFO. FIFO size is measured in bytes and is 4096. Table 5-8 lists the FIFO flag status.

Table 5-8. Data FIFO Flag Status

 

Data bytes in FIFO

 

Empty

 

Almost Full

 

Full

 

 

 

 

 

 

 

0

 

True

 

False

 

False

 

 

 

1 to (Threshold - 1)

 

False

 

False

 

False

 

 

 

Threshold to (FIFO size - 1)

 

False

 

True

 

False

 

 

 

FIFO size (4096)

 

False

 

True

 

True

 

 

 

 

 

 

 

 

 

 

 

 

5.2.2 Scan List Queue Register (base + 1)

The Scan List Queue Register is considered the access port to the scan list queue which can hold up to 2048 entries (each has two bytes). Each entry specifies an analog input channel and it’s associated gain as well as other settings.

Note: Although the scan list queue register is 8 bits wide, it is required that the register be accessed as a 16-bit word to guarantee integrity. The low byte (LSB or the least significant byte) should always be accessed first, followed by the high byte (MSB or the most significant byte). The bit definition is explained in Table 5-9.

Table 5-9. Scan List Queue Entry Bit Definition

 

Bit

Byte

Definition

Explanation

 

 

 

 

15

MSB

Reserved

as 0

 

 

 

14

MSB

Analog input mode

1/0 : differential/single-ended

 

 

 

13-12

MSB

Internal gain selection

00/01/10/11 : 1/2/4/8

 

 

 

11

MSB

Not in use

don’t care

 

 

 

10-8

MSB

Internal channel selection

0000..1111 : channel 0..7

 

 

 

7

LSB

Starting channel mark

Set to ‘1’ for the 1st entry in the

 

 

 

6

LSB

Reserved

for expansion cards (SSH)

 

 

 

5-4

LSB

External gain selection

00/01/10/11 : 1/2/4/8

 

 

 

3-0

LSB

External channel selection

0000..1111 : channel 0..7

 

 

 

 

 

 

 

 

 

DAQP-208/208H/308 Users Manual

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Contents Type II Pcmcia Data Acquisition Adapter s DAQP-208/208H/308WARRANTY/DISCLAIMER For immediate technical or application assistance Servicing North AmericaServicing Europe Page Page Table of Contents Page List of Figures and Tables Daqp Series Card Output ConnectorIntroduction Hardware Configuration and Initial Setup Page Software Installation Windows NT Page Data Acquisition Software and Drivers DAQPACL.SYS DAQPAEN.EXE Page Device = C\DAQPACL.SYS Device = C\DAQPACL.SYS b300,i5 Page Page Page Device = C\DAQPAEN.EXE S0,r GND DA0 DA1 Field WiringGND CP-DAQPA Cable AssemblyDaqp Series Card Cable Mapping UIO-37 Terminal Block UIO-37 Screw Terminal BlockTheory of Operation DC/DC Power SupplyProgrammable Gain Control Amplifier Analog Input MultiplexerScan List Register Trigger Circuit A/D Converter and Data Fifo Digital I/O Interrupt and StatusFifo A/D State Machine10 D/A Circuit Timer/CounterPage Pcmcia Interface O RegistersSreset Address Map Bit Page Data Fifo Threshold Setting LSB 1080 Select channel 0, gain 2, 1st entry Page Page Page Page Digital input bit External gain select, high bit All Output Flush scan list command High byte of the almost full threshold 15 2K option 18. D/A Data Port Bit Definition Bits Explanation 15-13 19. D/A Update Modes 20. Timer/Counter Modes Page Page Page Specifications TTL DAQP-208/208H/308 Version April 12