5.2.1.3 FIFO Flags
When reading the register under mode 1 or 3, the first available data byte from the data FIFO will be returned if it is not empty, otherwise the returned byte is not defined. The FIFO full flag will be cleared after the data FIFO register is read provided there are no more data bytes written into the FIFO by the A/D converter under mode 1 or 3. The same will happen to the FIFO almost full flag if the data bytes available in the FIFO are less than the almost full threshold. The FIFO empty flag will be set immediately after the last byte is read from the FIFO. FIFO size is measured in bytes and is 4096. Table
Table
| Data bytes in FIFO |
| Empty |
| Almost Full |
| Full |
| |
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| |||||
| 0 |
| True |
| False |
| False |
|
|
| 1 to (Threshold - 1) |
| False |
| False |
| False |
|
|
| Threshold to (FIFO size - 1) |
| False |
| True |
| False |
|
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| FIFO size (4096) |
| False |
| True |
| True |
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5.2.2 Scan List Queue Register (base + 1)
The Scan List Queue Register is considered the access port to the scan list queue which can hold up to 2048 entries (each has two bytes). Each entry specifies an analog input channel and it’s associated gain as well as other settings.
Note: Although the scan list queue register is 8 bits wide, it is required that the register be accessed as a
Table
| Bit | Byte | Definition | Explanation |
| |
|
| |||||
| 15 | MSB | Reserved | as 0 |
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| 14 | MSB | Analog input mode | 1/0 : |
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| MSB | Internal gain selection | 00/01/10/11 : 1/2/4/8 |
|
| |
| 11 | MSB | Not in use | don’t care |
|
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| MSB | Internal channel selection | 0000..1111 : channel 0..7 |
|
| |
| 7 | LSB | Starting channel mark | Set to ‘1’ for the 1st entry in the |
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| 6 | LSB | Reserved | for expansion cards (SSH) |
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| LSB | External gain selection | 00/01/10/11 : 1/2/4/8 |
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| |
| LSB | External channel selection | 0000..1111 : channel 0..7 |
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| |
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43 |