Figure 3-1. DAQP Series Card Output Connector | 21 |
Figure 3-2. CP-DAQPA/UIO-37 D37 Pin Diagram | 22 |
Figure 3-3. UIO-37 Terminal Block | 23 |
Figure 3-4. DAQP Card with Accessories | 24 |
Figure 4-1. Transition Diagram of A/D Conversion Process | 31 |
Figure 5-1. Pacer Clock Block Diagram | 46 |
Table 2-1. Comparison Between Client Driver and Enabler | 13 |
Table 3-1. DAQP Series Card Cable Mapping | 24 |
Table 5-1. PCMCIA Configuration Registers | 34 |
Table 5-2. COR Bit Definition | 35 |
Table 5-3. CCSR Bit Definition | 35 |
Table 5-4. DAQP Series Card Address Map | 36 |
Table 5-5. Data FIFO Register Bit Allocation | 37 |
Table 5-6. Data FIFO Operation Mode | 37 |
Table 5-7. Data FIFO Threshold Setting | 38 |
Table 5-8. Data FIFO Flag Status | 39 |
Table 5-9. Scan List Queue Entry Bit Definition | 39 |
Table 5-10. Scan List Queue Programming Example 1 | 40 |
Table 5-11. Scan List Queue Programming Example 2 | 40 |
Table 5-12. Control Register Bit Definition | 41 |
Table 5-13. Status Register Bit Definition | 44 |
Table 5-14. Digital Output Register Bit Definition | 45 |
Table 5-15. Digital Input Register Bit Definition | 45 |
Table 5-16. Command Register Bit Definition | 47 |
Table 5-17. Data FIFO Threshold Setting | 48 |
Table 5-18. D/A Data Port Bit Definition | 49 |
Table 5-19. D/A Update Modes | 50 |
Table 5-20. Timer/Counter Modes | 51 |
Table 5-21. Auxiliary Control Register Bit Definition | 53 |
Table 5-22. Auxiliary Status Register Bit Definition | 54 |
