5.2.8.2 Timer/Counter Clock Source
Bit 2 of the auxiliary control register (base + 15, write) selects the timer/counter clock source. The source can be either the internal 1 MHz clock (bit 2 is “0”) or the external clock (bit 2 is “1”). Because of the pin confinement, the timer/counter external clock input is shared with the A/D external clock input, which is also digital input bit 2. The external clock should have a minimum pulse width of 100 ns and a maximum frequency of 5 MHz.
5.2.8.3 Reading Timer/Counter Contents
The contents of the up-counter can be read “on the fly” by sending the read latch command. Upon receiving the command, the current content of the up-counter is latched into the read latch register. The timer/counter control logic guarantees the integrity of the latched value. The read latch operation works in all four timer/counter modes. The latched value in the read latch register will not change until next read latch command is received.
5.2.8.4 Timer Divisor/Counter Modulus
The up-counter always counts up from it’s initial value (determined by the reload register) to its final count (always 65535 or hexadecimal FFFF). “D” is the divisor (also called counter modulus) of the timer and “X” is the value written to the reload register. The relationship between the two is as follows:
D = 65536 - X
The up-counter counts up from X to 65535. D=1 or X=65535 should be avoided because the up-counter will stick with these values.
5.2.8.5 Timer/Counter Overflow
When the timer/counter reaches it’s final count of 65535, the next rising edge of the selected clock source will reload the up-counter from the reload register and set the timer/counter overflow event latch to “1” (bit 4 of the auxiliary status register). This will cause an interrupt if the timer/counter interrupt is enabled (bit 5 of the auxiliary control register set to “1”). The overflow event latch can only be cleared by writing a “0” to bit 5 of the auxiliary control register. Reading the auxiliary status register will not clear the timer/counter overflow event latch.
The timer/counter output will be “1” for one clock cycle as the timer/counter overflows after reaching the final value of 65535. If the timer/counter is paused or stuck at the final count, the output pin will then be high as long as the final count holds.
The timer/counter is totally independent of the pacer clock, which is dedicated to generating the sample rate for the A/D converter in continuous trigger mode. The timer/counter can be used for the D/A converter to synchronize its channel output update.
