Omega 208H, DAQP-208, 308 user manual Bit

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5.2.1 Data FIFO Register (base + 0)

The data FIFO register is considered as the access port to the data FIFO, which holds up to 2048 data words from the A/D conversion results. The port is also used for programming the data FIFO thresholds, as explained later in this section.

Note: Although the data FIFO register is 8 bits wide, it is strongly recommended that the register be accessed as a 16 bit word to guarantee integrity. The low byte (LSB or the least significant byte) should always be accessed first, followed by the high byte (MSB or the most significant byte). Two consecutive bytes should be read from or written into the port each time it is accessed. The following table illustrates bit allocation.

Table 5-5. Data FIFO Register Bit Allocation

 

 

Bit 7

 

Bit 6

 

Bit 5

 

Bit 4

 

Bit 3

 

Bit 2

 

Bit 1

 

Bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSB

D7

 

D6

 

D5

 

D4

 

D3

 

D2

 

D1

 

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSB

D15

 

D14

 

D13

 

D12

 

D11

 

D10

 

D9

 

D8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5.2.1.1 Data FIFO Operation Modes

Depending on the mode of operation, the 16-bit word read from or written into the register has different meanings as shown in the following table.

Table 5-6. Data FIFO Operation Mode

 

Mod

 

Selection Bit

 

A/D

 

Acces

 

Operation

 

 

 

 

 

 

 

 

e

 

 

 

 

 

s

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0, threshold

 

Idle

 

Read

 

Verify data FIFO threshold

 

 

 

 

 

 

 

 

 

Write

 

Program data FIFO threshold

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1, data FIFO

 

Idle

 

Read

 

Read data FIFO

 

 

 

 

 

 

 

 

 

Write

 

Write data FIFO (diagnosis)

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

0, threshold

 

Run

 

Read

 

Verify data FIFO threshold

 

 

 

 

 

 

 

 

 

Write

 

Not allowed

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

1, data FIFO

 

Run

 

Read

 

Read data FIFO

 

 

 

 

 

 

 

 

 

Write

 

Not allowed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The “selection bit” is also called the “program/access” control bit, as defined in the auxiliary control register (base + 7). Mode 0 is the FIFO program mode, under which the two consecutive words (four bytes) written into the register address will set the almost full and

DAQP-208/208H/308 Users Manual

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Contents DAQP-208/208H/308 Type II Pcmcia Data Acquisition Adapter sWARRANTY/DISCLAIMER For immediate technical or application assistance Servicing North AmericaServicing Europe Page Page Table of Contents Page Daqp Series Card Output Connector List of Figures and TablesIntroduction Hardware Configuration and Initial Setup Page Software Installation Windows NT Page Data Acquisition Software and Drivers DAQPACL.SYS DAQPAEN.EXE Page Device = C\DAQPACL.SYS Device = C\DAQPACL.SYS b300,i5 Page Page Page Device = C\DAQPAEN.EXE S0,r Field Wiring GND DA0 DA1CP-DAQPA Cable Assembly GNDDaqp Series Card Cable Mapping UIO-37 Screw Terminal Block UIO-37 Terminal BlockDC/DC Power Supply Theory of OperationAnalog Input Multiplexer Programmable Gain Control AmplifierScan List Register Trigger Circuit A/D Converter and Data Fifo Interrupt and Status Digital I/OA/D State Machine FifoTimer/Counter 10 D/A CircuitPage O Registers Pcmcia InterfaceSreset Address Map Bit Page Data Fifo Threshold Setting LSB 1080 Select channel 0, gain 2, 1st entry Page Page Page Page Digital input bit External gain select, high bit All Output Flush scan list command High byte of the almost full threshold 15 2K option 18. D/A Data Port Bit Definition Bits Explanation 15-13 19. D/A Update Modes 20. Timer/Counter Modes Page Page Page Specifications TTL DAQP-208/208H/308 Version April 12