5.2.1 Data FIFO Register (base + 0)
The data FIFO register is considered as the access port to the data FIFO, which holds up to 2048 data words from the A/D conversion results. The port is also used for programming the data FIFO thresholds, as explained later in this section.
Note: Although the data FIFO register is 8 bits wide, it is strongly recommended that the register be accessed as a 16 bit word to guarantee integrity. The low byte (LSB or the least significant byte) should always be accessed first, followed by the high byte (MSB or the most significant byte). Two consecutive bytes should be read from or written into the port each time it is accessed. The following table illustrates bit allocation.
Table
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| Bit 7 |
| Bit 6 |
| Bit 5 |
| Bit 4 |
| Bit 3 |
| Bit 2 |
| Bit 1 |
| Bit 0 |
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| LSB | D7 |
| D6 |
| D5 |
| D4 |
| D3 |
| D2 |
| D1 |
| D0 |
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| MSB | D15 |
| D14 |
| D13 |
| D12 |
| D11 |
| D10 |
| D9 |
| D8 |
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5.2.1.1 Data FIFO Operation Modes
Depending on the mode of operation, the
Table
| Mod |
| Selection Bit |
| A/D |
| Acces |
| Operation |
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| 0 |
| 0, threshold |
| Idle |
| Read |
| Verify data FIFO threshold |
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| Write |
| Program data FIFO threshold |
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| 1 |
| 1, data FIFO |
| Idle |
| Read |
| Read data FIFO |
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| Write |
| Write data FIFO (diagnosis) |
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| 2 |
| 0, threshold |
| Run |
| Read |
| Verify data FIFO threshold |
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| Write |
| Not allowed |
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| 3 |
| 1, data FIFO |
| Run |
| Read |
| Read data FIFO |
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| Write |
| Not allowed |
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The “selection bit” is also called the “program/access” control bit, as defined in the auxiliary control register (base + 7). Mode 0 is the FIFO program mode, under which the two consecutive words (four bytes) written into the register address will set the almost full and
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