Omega Speaker Systems PCI-DAS1002 manual 1 DAC0 Data Register, BADR4 +, 2 DAC1 Data Register

Page 34

7.6 BADR4

The I/O Region defined by BADR4 contains the DAC0 and DAC1 data registers.

7.6.1 DAC0 DATA REGISTER

BADR4 + 0

WRITE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

-

-

-

DAC0(11)

DAC0(10)

DAC0(9)

DAC0(8)

DAC0(7)

DAC0(6)

DAC0(5)

DAC0(4)

DAC0(3)

DAC0(2)

DAC0(1)

DAC0(0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSB

 

 

 

 

 

 

 

 

 

 

LSB

Writing to this register will initiate data conversion on DAC0. If the MODE bit in BADR1+8

is set, writes to this register will provide a simultaneous update of both DAC0 and DAC1 with the data written to this regis- ter. The data format is dependent upon the offset mode described below:

Bipolar Mode: Offset Binary Coding

000 h = -FS

7FFh = Mid-scale (0V)

FFFh = +FS - 1LSB

Unipolar Mode: Straight Binary Coding

000 h = -FS (0V)

7FFh = Mid-scale (+FS/2)

FFFh = +FS - 1LSB

7.6.2 DAC1 DATA REGISTER

BADR4 + 2

WRITE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

-

-

-

DAC1(11)

DAC1(10)

DAC1(9)

DAC1(8)

DAC1(7)

DAC1(6)

DAC1(5)

DAC1(4)

DAC1(3)

DAC1(2)

DAC1(1)

DAC1(0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSB

 

 

 

 

 

 

 

 

 

 

LSB

Writing to this register will initiate data conversion on DAC1. If the MODE bit in BADR1+8 is set, writes to this register will have no effect

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Contents Users Guide Table of Contents BADR3 BADR0 BADR1BADR2 BADR4Introduction Installation IntroductionRUN InstaCal DOS and/or WindowsConnector PIN Diagram Hardware ConnectionsSingle-Ended and Differential Inputs Analog ConnectionsSingle-Ended Inputs Differential Input Differential InputsSystem Grounds and Isolation Which system do you have?Small Common Mode Voltages Systems with Common Mode ground offset VoltagesLarge Common Mode Voltages PCI-DAS1000 and signal source already have isolated grounds Ground Category Input Configuration Our view    Board Board Programming & Software Applications SELF-CALIBRATION of the PCI-DAS1000 Analog InputsAnalog Outputs Interrupt / ADC Fifo Register BADR0BADR1 Region Function OperationsIntcl InteEoaie AdflclADC Channel MUX and Control Register BADR1 + CHL8-CHL1, CHH8-CHH1Pacer Source EOC= ADC Done = ADC Busy TS10 Trigger CONTROL/STATUS Register BADR1 +ARM Xtrig Fifo Mode Sample CTRC0SRC IndxgtDAC Channel Cal Function Calibration RegisterBADR1 + Cal SourceDACnR10 Dacen ModeDAC CONTROL/STATUS Register BADR1 + DACnR1 DACnR0 Range LSB SizeADC Fifo Clear Register BADR2 + BADR2ADC Data Register BADR2 + MSB LSBBADR3 + BADR3ADC Pacer Clock Data and Control Registers Device Counter # FunctionDIO Port a Data ADC 8254 Control RegisterDigital I/O Data and Control Registers DIO Port B Data DIO Control Register DIO Port C Data Port a Port C Port B Upper Lower OUT 8254B Counter 2 Data User Counter #6 Index and User Counter 4 Data and Control Registers8254B Counter 1 Data User Counter #5 BADR3 + Ah8254B Control Register BADR3 + BhBADR4 + BADR41 DAC0 Data Register 2 DAC1 Data RegisterElectrical Specifications Analog Output Power consumption EnvironmentalEC Declaration of Conformity
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