Omega Speaker Systems PCI-DAS1002 Index and User Counter 4 Data and Control Registers, BADR3 + Ah

7.5.3 INDEX and USER COUNTER 4 DATA AND CONTROL REGISTERS

8254B COUNTER 0 DATA - ADC PRE-TRIGGER INDEX COUNTER(or user counter 4)

BADR3 + 8

READ/WRITE

7	6	5	4	2	3	1	0
D7	D6	D5	D4	D3	D2	D1	D0

Counter 0 of the 8254B device is a shared resource on the PCI-DAS1000. When not in ADC pre-trigger mode, the clock, gate and output lines of Counter 0 are available to the user at the 100 pin connector as user counter 4. The 8254's Counter 0 clock source is SW selectable via the C0SRC bit in BADR1+4.

When in ADC Pre-trigger mode, this counter is used as the ADC Pre-Trigger index counter. This counter serves to mark the boundary between pre- and post-trigger samples when the ADC is operating in Pre-Trigger Mode. The External ADC Trigger flip flop gates Counter 0 on; the ADC FIFO Half-Full signal gates it off. Knowing the desired number of post- trigger samples, software can then calculate how may 1/2 FIFO data packets need to be collected and what corresponding residual sample count needs to be written to BADR3 + 0.

8254B COUNTER 1 DATA - USER COUNTER #5

BADR3 + 9

READ/WRITE

7	6	5	4	2	3	1	0
D7	D6	D5	D4	D3	D2	D1	D0

The clock, gate and output lines of Counter 1 are available to the user at the 100 pin connector as user counter 5. The 8254's Counter 1 clock source is always external and must be provided by the user. The buffered version of the internal 10MHz clock available at the user connector may be used as the

clock source.

8254B COUNTER 2 DATA - USER COUNTER #6

BADR3 + Ah

READ/WRITE

7	6	5	4	2	3	1	0
D7	D6	D5	D4	D3	D2	D1	D0

The clock, gate and output lines of Counter 2 are available to the user at the 100 pin connector as user counter 6. The 8254's Counter 2 clock source is always external and must be provided by the user. The buffered version of the internal 10MHz clock available at the user connector may be used as the clock source.

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