8.4 COUNTER SECTION
Counter type | 82C54 |
Configuration | Two 82C54 devices. 3 down counters per 82C54, 16 bits each |
| 82C54A: |
| Counter 0 | - ADC residual sample counter. | |
| Source: | ADC Clock. | |
| Gate: |
| Internal programmable source. |
| Output: | ||
| Counter 1 | - ADC Pacer Lower Divider | |
| Source: | 10 MHz oscillator | |
| Gate: |
| Tied to Counter 2 gate, programmable source. |
| Output: | Chained to Counter 2 Clock. | |
| Counter 2 - ADC Pacer Upper Divider | ||
| Source: | Counter 1 Output. | |
| Gate: |
| Tied to Counter 1 gate, programmable source. |
| Output: | ADC Pacer clock (if software selected), available at connector | |
| 82C54B: |
|
|
| Counter 0 - Pretrigger Mode | ||
| Source: | ADC Clock. | |
| Gate: |
| External trigger |
| Output: | ||
| Counter 0 | - User Counter 4 (when in | |
| Source: | User input at 100pin connector (CLK4) or internal 10MHz | |
|
|
| (software selectable) |
| Gate: |
| User input at 100pin connector (GATE4). |
| Output: | Available at 100pin connector (OUT4). | |
| Counter 1 | - User Counter 5 | |
| Source: | User input at 100pin connector (CLK5). | |
| Gate: |
| User input at 100pin connector (GATE5). |
| Output: | Available at 100pin connector (OUT5). | |
| Counter 2 | - User Counter 6 | |
| Source: | User input at 100pin connector (CLK6). | |
| Gate: |
| User input at 100pin connector (GATE6). |
| Output: | Available at 100pin connector (OUT6). | |
Clock input frequency | 10Mhz max |
| |
High pulse width (clock input) | 30ns min |
| |
Low pulse width (clock input) | 50ns min |
| |
Gate width high or low | 50ns min |
| |
Input low voltage | 0.8V max |
| |
Input high voltage | 2.0V min |
| |
Output low voltage | 0.4V max |
| |
Output high voltage | 3.0V min |
|
8.5 OTHER SPECIFICATIONS
Power consumption
+5V Operating (A/D converting to FIFO) 0.8A typical, 1.0A max
Environmental |
|
Operating temperature range | 0 to 70°C |
Storage temperature range | |
Humidity | 0 to 90% |
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