Omega Speaker Systems PCI-DAS1001, PCI-DAS1002 manual C0SRC, Xtrig, Indxgt, Fifo Mode Sample CTR

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The table below provides a summary of bit settings and operation.

				PRTRG				FFM0					ARM is set...							FIFO Mode					Sample CTR
																									Starts on...

				0				0					Via SW when						# Samples >1 FIFO
											remaining count <1024									Normal Mode
												------------------------						----------------------------------								ADHF
												Via SW immediately						1/2 FIFO < # Samples < 1 FIFO
																				Normal Mode

				0				1				Via SW immediately							# Samples <1/2 FIFO						ADC Pacer
																				Normal Mode

				1				0					Via SW when						# Samples >1 FIFO
											remaining count <1024								Pre-Trigger Mode
												------------------------						----------------------------------								ADHF
												Via SW immediately						1/2 FIFO < # Samples < 1 FIFO
																			Pre-Trigger Mode

				1				1				Via SW immediately							# Samples <1/2 FIFO,							XTRIG
																			Pre-Trigger Mode
C0SRC

						This bit allows the user to select the clock source for user Counter 0.
						1 = Internal 10MHz oscillator
						0 = External clock source input via CTR0CLK pin on 100p connector.
READ
15		14			13		12			11			10	9		8		7	6		5	4		3	2		1		0

-		-				-	INDX_GT			-			-	-		-		XTRIG	-		-	-		-	-		-		-

XTRIG						1 = External Trigger flip-flop has been set. This bit is write-cleared.
						0 = External Trigger flip-flop reset. No trigger has been received.

INDX_GT

1 = Pre-trigger index counter has completed its count.

0 = Pre-trigger index counter has not been gated on or has not yet completed its count.

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Contents Users Guide Table of Contents BADR2 BADR0 BADR1BADR3 BADR4Introduction Introduction InstallationDOS and/or Windows RUN InstaCalHardware Connections Connector PIN DiagramSingle-Ended and Differential Inputs Analog ConnectionsSingle-Ended Inputs Differential Inputs Differential InputWhich system do you have? System Grounds and IsolationSmall Common Mode Voltages Systems with Common Mode ground offset VoltagesLarge Common Mode Voltages Ground Category Input Configuration Our view PCI-DAS1000 and signal source already have isolated grounds Board Board Programming & Software Applications Analog Inputs SELF-CALIBRATION of the PCI-DAS1000Analog Outputs BADR1 BADR0Interrupt / ADC Fifo Register Region Function OperationsEoaie InteIntcl AdflclCHL8-CHL1, CHH8-CHH1 ADC Channel MUX and Control Register BADR1 +Pacer Source EOC= ADC Done = ADC Busy TS10 Trigger CONTROL/STATUS Register BADR1 +ARM C0SRC Fifo Mode Sample CTRXtrig IndxgtBADR1 + Calibration RegisterDAC Channel Cal Function Cal SourceDAC CONTROL/STATUS Register BADR1 + Dacen ModeDACnR10 DACnR1 DACnR0 Range LSB SizeADC Data Register BADR2 + BADR2ADC Fifo Clear Register BADR2 + MSB LSBADC Pacer Clock Data and Control Registers BADR3BADR3 + Device Counter # FunctionDigital I/O Data and Control Registers ADC 8254 Control RegisterDIO Port a Data DIO Port B DataDIO Control Register DIO Port C DataPort a Port C Port B Upper Lower OUT 8254B Counter 1 Data User Counter #5 Index and User Counter 4 Data and Control Registers8254B Counter 2 Data User Counter #6 BADR3 + AhBADR3 + Bh 8254B Control Register1 DAC0 Data Register BADR4BADR4 + 2 DAC1 Data RegisterElectrical Specifications Analog Output Environmental Power consumptionEC Declaration of Conformity