Omega Speaker Systems PCI-DAS1001 manual DAC CONTROL/STATUS Register BADR1 +, Dacen Mode, DACnR10

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7.3.5DAC CONTROL/STATUS REGISTER BADR1 + 8

This register selects the DAC gain/range and update modes. This is a Write-only register.

WRITE

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

-	-	-	-	DAC1R1	DAC1R0	DAC0R1	DAC0R0	MODE	-	-	-	-	-	DACEN	-

DACEN

MODE

DACnR[1:0]

This bit enables the Analog Out features of the board. 1 = DAC0/1 enabled.

0 = DAC0/1 disabled.

The power-on state of this bit is 0.

This bit determines the analog output mode of operation.

1 = Both DAC0 and DAC1 updated with data written to DAC0 data register. 0 = DACn updated with data written to DACn data register.

The power-on state of this bit is 0.

These bits select the independent gains/ranges for either DAC0 or DAC1. n=0 for DAC0 and n=1 for DAC1.

DACnR1	DACnR0	Range	LSB Size

0	0	Bipolar 5V	2.44mV

0	1	Bipolar 10V	4.88mV

1	0	Unipolar 5V	610uV

1	1	Unipolar 10V	1.22mV

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Contents Users Guide Table of Contents BADR4 BADR0 BADR1BADR2 BADR3Introduction Introduction InstallationDOS and/or Windows RUN InstaCalHardware Connections Connector PIN DiagramAnalog Connections Single-Ended and Differential InputsSingle-Ended Inputs Differential Inputs Differential InputWhich system do you have? System Grounds and IsolationSystems with Common Mode ground offset Voltages Small Common Mode VoltagesLarge Common Mode Voltages Ground Category Input Configuration Our view PCI-DAS1000 and signal source already have isolated grounds Board Board Programming & Software Applications Analog Inputs SELF-CALIBRATION of the PCI-DAS1000Analog Outputs Region Function Operations BADR0BADR1 Interrupt / ADC Fifo RegisterAdflcl InteEoaie IntclCHL8-CHL1, CHH8-CHH1 ADC Channel MUX and Control Register BADR1 +EOC Pacer Source= ADC Done = ADC Busy Trigger CONTROL/STATUS Register BADR1 + TS10ARM Indxgt Fifo Mode Sample CTRC0SRC XtrigCal Source Calibration RegisterBADR1 + DAC Channel Cal FunctionDACnR1 DACnR0 Range LSB Size Dacen ModeDAC CONTROL/STATUS Register BADR1 + DACnR10MSB LSB BADR2ADC Data Register BADR2 + ADC Fifo Clear Register BADR2 +Device Counter # Function BADR3ADC Pacer Clock Data and Control Registers BADR3 +DIO Port B Data ADC 8254 Control RegisterDigital I/O Data and Control Registers DIO Port a DataDIO Port C Data DIO Control RegisterPort a Port C Port B Upper Lower OUT BADR3 + Ah Index and User Counter 4 Data and Control Registers8254B Counter 1 Data User Counter #5 8254B Counter 2 Data User Counter #6BADR3 + Bh 8254B Control Register2 DAC1 Data Register BADR41 DAC0 Data Register BADR4 +Electrical Specifications Analog Output Environmental Power consumptionEC Declaration of Conformity