Omega Speaker Systems PCI-DAS1001, PCI-DAS1002 manual Eoc, Pacer Source, = ADC Done = ADC Busy

Page 23

The following tables summarizes all possible Offset/Range configurations:

PCI-DAS1002

UNIBIP

GS1

GS0

Input Range

Input Gain

Measurement

 

 

 

 

 

Resolution

 

 

 

 

 

 

0

0

0

±10V

1

4.88 mV

 

 

 

 

 

 

0

0

1

± 5V

2

2.44 mV

 

 

 

 

 

 

0

1

0

±2.5V

4

1.22 mV

 

 

 

 

 

 

0

1

1

±1.25V

8

610 uV

 

 

 

 

 

 

1

0

0

0-10V

1

2.44 mV

 

 

 

 

 

 

1

0

1

0-5V

2

1.22 mV

 

 

 

 

 

 

1

1

0

0-2.5V

4

610 uV

 

 

 

 

 

 

1

1

1

0-1.25V

8

305 uV

 

 

 

 

 

 

 

 

 

 

 

 

PCI-DAS1001

UNIBIP

GS1

GS0

Input Range

Input Gain

Measurement

 

 

 

 

 

Resolution

 

 

 

 

 

 

0

0

0

±10V

1

4.88 mV

 

 

 

 

 

 

0

0

1

± 1V

10

488 uV

 

 

 

 

 

 

0

1

0

±0.1V

100

48.8 uV

 

 

 

 

 

 

0

1

1

±0.01V

1,000

4.88 uV

 

 

 

 

 

 

1

0

0

0-10V

1

2.44 mV

 

 

 

 

 

 

1

0

1

0-1V

10

244 uV

 

 

 

 

 

 

1

1

0

0-0.1V

100

24.4 uV

 

 

 

 

 

 

1

1

1

0-0.01V

1,000

2.44 uV

 

 

 

 

 

 

 

 

 

 

 

 

ADPS[1:0] These bits select the ADC Pacer Source. Maximum Internal/External Pacer frequency is 330KHz.

 

 

 

 

 

 

ADPS1

 

 

ADPS0

 

 

 

Pacer Source

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

0

 

 

 

 

SW Convert

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

1

 

 

 

82C54 Counter/Timer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

0

 

 

 

 

External Falling

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

1

 

 

 

 

External Rising

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: For ADPS[1:0] = 00 case, SW conversions are initiated

 

 

 

 

 

 

 

 

 

via a word write to BADR2 + 0. Data is 'don't care.'

 

 

 

 

 

 

 

READ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

 

11

 

10

9

8

 

7

 

6

 

5

 

4

 

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

EOC

-

-

 

-

 

-

-

-

 

-

 

-

 

-

 

-

 

-

 

-

-

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EOC

 

Real-time, non-latched status of ADC End-of-Conversion signal.

 

 

 

 

 

 

 

1 = ADC DONE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = ADC BUSY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

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Page 22 Page 24
Contents Users Guide Table of Contents BADR4 BADR0 BADR1BADR2 BADR3Introduction Introduction InstallationDOS and/or Windows RUN InstaCalHardware Connections Connector PIN DiagramSingle-Ended Inputs Analog ConnectionsSingle-Ended and Differential Inputs Differential Inputs Differential InputWhich system do you have? System Grounds and IsolationLarge Common Mode Voltages Systems with Common Mode ground offset VoltagesSmall Common Mode Voltages Ground Category Input Configuration Our view PCI-DAS1000 and signal source already have isolated grounds    Board Board Programming & Software Applications Analog Inputs SELF-CALIBRATION of the PCI-DAS1000Analog Outputs Region Function Operations BADR0BADR1 Interrupt / ADC Fifo RegisterAdflcl InteEoaie IntclCHL8-CHL1, CHH8-CHH1 ADC Channel MUX and Control Register BADR1 += ADC Done = ADC Busy EOCPacer Source ARM Trigger CONTROL/STATUS Register BADR1 +TS10 Indxgt Fifo Mode Sample CTRC0SRC XtrigCal Source Calibration RegisterBADR1 + DAC Channel Cal FunctionDACnR1 DACnR0 Range LSB Size Dacen ModeDAC CONTROL/STATUS Register BADR1 + DACnR10MSB LSB BADR2ADC Data Register BADR2 + ADC Fifo Clear Register BADR2 +Device Counter # Function BADR3ADC Pacer Clock Data and Control Registers BADR3 +DIO Port B Data ADC 8254 Control RegisterDigital I/O Data and Control Registers DIO Port a DataPort a Port C Port B Upper Lower OUT DIO Port C DataDIO Control Register BADR3 + Ah Index and User Counter 4 Data and Control Registers8254B Counter 1 Data User Counter #5 8254B Counter 2 Data User Counter #6BADR3 + Bh 8254B Control Register2 DAC1 Data Register BADR41 DAC0 Data Register BADR4 +Electrical Specifications Analog Output Environmental Power consumptionEC Declaration of Conformity
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