Omega Speaker Systems PCI-DAS1002 ADC Data Register BADR2 +, ADC Fifo Clear Register BADR2 +

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7.4 BADR2

The I/O Region defined by BADR2 contains the ADC Data register and the ADC FIFO clear

register.

7.4.1ADC DATA REGISTER BADR2 + 0

ADC Data register.

WRITE

Writing to this register is only valid for SW initiated conversions. The ADC Pacer source must be set to 00 via the ADPS[1:0] bits. A null write to BADR2 + 0 will begin a single conversion. Conversion status may be determined in two ways. The EOC bit in BADR1 + 0 may be polled until true or ADNEI (the AD FIFO not-empty interrupt) may be used to signal that the ADC conversion is complete and the data word is present in the FIFO.

READ

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

0	0	0	0	AD11	AD10	AD9	AD8	AD7	AD6	AD5	AD4	AD3	AD2	AD1	AD0

				MSB											LSB

AD[11:0] This register contains the current ADC data word. Data format is dependent upon offset mode:

Bipolar Mode: Offset Binary Coding

000 h = -FS

7FFh = Mid-scale (0V)

FFFh = +FS - 1LSB

Unipolar Mode: Straight Binary Coding

000 h = -FS (0V)

7FFh = Mid-scale (+FS/2)

FFFh = +FS - 1LSB

7.4.2ADC FIFO CLEAR REGISTER BADR2 + 2

ADC FIFO Clear register. A Write-only register. A write to this address location clears the ADC FIFO. Data is don't care. The ADC FIFO should be cleared before all new ADC operations.

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Contents Users Guide Table of Contents BADR0 BADR1 BADR2BADR3 BADR4Introduction Installation IntroductionRUN InstaCal DOS and/or WindowsConnector PIN Diagram Hardware ConnectionsSingle-Ended and Differential Inputs Analog ConnectionsSingle-Ended Inputs Differential Input Differential InputsSystem Grounds and Isolation Which system do you have?Small Common Mode Voltages Systems with Common Mode ground offset VoltagesLarge Common Mode Voltages PCI-DAS1000 and signal source already have isolated grounds Ground Category Input Configuration Our view Board Board Programming & Software Applications SELF-CALIBRATION of the PCI-DAS1000 Analog InputsAnalog Outputs BADR0 BADR1Interrupt / ADC Fifo Register Region Function OperationsInte EoaieIntcl AdflclADC Channel MUX and Control Register BADR1 + CHL8-CHL1, CHH8-CHH1Pacer Source EOC= ADC Done = ADC Busy TS10 Trigger CONTROL/STATUS Register BADR1 +ARM Fifo Mode Sample CTR C0SRCXtrig IndxgtCalibration Register BADR1 +DAC Channel Cal Function Cal SourceDacen Mode DAC CONTROL/STATUS Register BADR1 +DACnR10 DACnR1 DACnR0 Range LSB SizeBADR2 ADC Data Register BADR2 +ADC Fifo Clear Register BADR2 + MSB LSBBADR3 ADC Pacer Clock Data and Control RegistersBADR3 + Device Counter # FunctionADC 8254 Control Register Digital I/O Data and Control RegistersDIO Port a Data DIO Port B DataDIO Control Register DIO Port C DataPort a Port C Port B Upper Lower OUT Index and User Counter 4 Data and Control Registers 8254B Counter 1 Data User Counter #58254B Counter 2 Data User Counter #6 BADR3 + Ah8254B Control Register BADR3 + BhBADR4 1 DAC0 Data RegisterBADR4 + 2 DAC1 Data RegisterElectrical Specifications Analog Output Power consumption EnvironmentalEC Declaration of Conformity