7.4 BADR2
The I/O Region defined by BADR2 contains the ADC Data register and the ADC FIFO clear
register.
7.4.1ADC DATA REGISTER BADR2 + 0
ADC Data register.
WRITE
Writing to this register is only valid for SW initiated conversions. The ADC Pacer source must be set to 00 via the ADPS[1:0] bits. A null write to BADR2 + 0 will begin a single conversion. Conversion status may be determined in two ways. The EOC bit in BADR1 + 0 may be polled until true or ADNEI (the AD FIFO
READ
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0 | 0 | 0 | 0 | AD11 | AD10 | AD9 | AD8 | AD7 | AD6 | AD5 | AD4 | AD3 | AD2 | AD1 | AD0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| MSB |
|
|
|
|
|
|
|
|
|
| LSB |
AD[11:0] This register contains the current ADC data word. Data format is dependent upon offset mode:
Bipolar Mode: Offset Binary Coding
000 h =
7FFh =
FFFh = +FS - 1LSB
Unipolar Mode: Straight Binary Coding
000 h =
7FFh =
FFFh = +FS - 1LSB
7.4.2ADC FIFO CLEAR REGISTER BADR2 + 2
ADC FIFO Clear register. A
25