Omega Speaker Systems PCI-DAS1001, PCI-DAS1002 manual BADR0 BADR1, BADR2, BADR3, BADR4

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7.0 PCI-DAS1000 REGISTER DESCRIPTION	17
7.1 REGISTER OVERVIEW	17
7.2 BADR0	17
7.3 BADR1	17
7.3.1 INTERRUPT / ADC FIFO REGISTER	17
7.3.2 ADC CHANNEL MUX AND CONTROL REGISTER	19
7.3.3 TRIGGER CONTROL/STATUS REGISTER	21
7.3.4 CALIBRATION REGISTER	23
7.3.5 DAC CONTROL/STATUS REGISTER	24
7.4 BADR2	25
7.4.1 ADC DATA REGISTER	25
7.4.2 ADC FIFO CLEAR REGISTER	25
7.5 BADR3	26
7.5.1 ADC PACER CLOCK DATA AND CONTROL REGISTERS	26
7.5.2 DIGITAL I/O DATA AND CONTROL REGISTERS	27
7.5.3 INDEX AND USER COUNTER 4 DATA AND CONTROL REGISTERS . 29
7.6 BADR4	31
7.6.1 DAC0 DATA REGISTER	31
7.6.2 DAC1 DATA REGISTER	31
8.0 ELECTRICAL SPECIFICATIONS	32
8.1 ANALOG INPUT SECTION	32
8.2 ANALOG OUTPUT	33
8.3 PARAELLEL DIGITAL INPUT/OUTPUT	33
8.4 COUNTER SECTION	34
8.5 OTHER SPECIFICATIONS	34

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Contents Users Guide Table of Contents BADR4 BADR0 BADR1BADR2 BADR3Introduction Introduction InstallationDOS and/or Windows RUN InstaCalHardware Connections Connector PIN DiagramAnalog Connections Single-Ended and Differential InputsSingle-Ended Inputs Differential Inputs Differential InputWhich system do you have? System Grounds and IsolationSystems with Common Mode ground offset Voltages Small Common Mode VoltagesLarge Common Mode Voltages Ground Category Input Configuration Our view PCI-DAS1000 and signal source already have isolated grounds Board Board Programming & Software Applications Analog Inputs SELF-CALIBRATION of the PCI-DAS1000Analog Outputs Region Function Operations BADR0BADR1 Interrupt / ADC Fifo RegisterAdflcl InteEoaie IntclCHL8-CHL1, CHH8-CHH1 ADC Channel MUX and Control Register BADR1 +EOC Pacer Source= ADC Done = ADC Busy Trigger CONTROL/STATUS Register BADR1 + TS10ARM Indxgt Fifo Mode Sample CTRC0SRC XtrigCal Source Calibration RegisterBADR1 + DAC Channel Cal FunctionDACnR1 DACnR0 Range LSB Size Dacen ModeDAC CONTROL/STATUS Register BADR1 + DACnR10MSB LSB BADR2ADC Data Register BADR2 + ADC Fifo Clear Register BADR2 +Device Counter # Function BADR3ADC Pacer Clock Data and Control Registers BADR3 +DIO Port B Data ADC 8254 Control RegisterDigital I/O Data and Control Registers DIO Port a DataDIO Port C Data DIO Control RegisterPort a Port C Port B Upper Lower OUT BADR3 + Ah Index and User Counter 4 Data and Control Registers8254B Counter 1 Data User Counter #5 8254B Counter 2 Data User Counter #6BADR3 + Bh 8254B Control Register2 DAC1 Data Register BADR41 DAC0 Data Register BADR4 +Electrical Specifications Analog Output Environmental Power consumptionEC Declaration of Conformity

7.2 BADR0

7.3 BADR1

7.4 BADR2

7.5 BADR3

7.6 BADR4