Omega Speaker Systems PCI-DAS1002 manual Calibration Register, BADR1 +, DAC Channel Cal Function

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7.3.4 CALIBRATION REGISTER

See "Calibrating The PCI-DAS1000"document for additional programming details.

BADR1 + 6

This register controls all autocal operations. This is a Write-only register.

WRITE

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

SDI	CALEN	CSRC2	CSRC1	CSRC0	-	SEL7376	SEL8800	-	-	-	-	-	-	-	-

SEL8800 This bit enables the 8-bit trim DACs for the following circuits:

DAC Channel	Cal Function

0	DAC0 Fine Gain

1	DAC0 Coarse Gain

2	DAC0 Offset

3	DAC1 Offset

4	DAC1 Fine Gain

5	DAC1 Coarse Gain

6	ADC Coarse Offset

7	ADC Fine Offset

SEL7376 This bit latches the 7-bit serial data stream into the AD7376 digital potentiometer (10KOhm). The AD7376 is used for analog front-end gain calibration.

CSRC[2:0] These bits select the different calibration sources available to the ADC front end.

CSRC2	CSRC1	CSRC0	Cal Source

0	0	0	AGND

0	0	1	7.0V

0	1	0	3.5V

0	1	1	1.75V

1	0	0	0.875V

1	0	1	8.6mV

1	1	0	VDAC0

1	1	1	VDAC1

CALEN This bit is used to enable Cal Mode.

1 = Selected Cal Source, CSRC[2:0], is fed into Analog Channel 0. 0 = Analog Channel 0 functions as normal input.

SDI Serial Data In. This bit is used to set serial address/data stream for the DAC8800 TrimDac and 7376 digital potentiometer. Used in conjunction with SEL8800 and SEL7376 bits.

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Contents Users Guide Table of Contents BADR3 BADR0 BADR1BADR2 BADR4Introduction Installation IntroductionRUN InstaCal DOS and/or WindowsConnector PIN Diagram Hardware ConnectionsSingle-Ended Inputs Analog ConnectionsSingle-Ended and Differential Inputs Differential Input Differential InputsSystem Grounds and Isolation Which system do you have?Large Common Mode Voltages Systems with Common Mode ground offset VoltagesSmall Common Mode Voltages PCI-DAS1000 and signal source already have isolated grounds Ground Category Input Configuration Our view Board Board Programming & Software Applications SELF-CALIBRATION of the PCI-DAS1000 Analog InputsAnalog Outputs Interrupt / ADC Fifo Register BADR0BADR1 Region Function OperationsIntcl InteEoaie AdflclADC Channel MUX and Control Register BADR1 + CHL8-CHL1, CHH8-CHH1= ADC Done = ADC Busy EOCPacer Source ARM Trigger CONTROL/STATUS Register BADR1 +TS10 Xtrig Fifo Mode Sample CTRC0SRC IndxgtDAC Channel Cal Function Calibration RegisterBADR1 + Cal SourceDACnR10 Dacen ModeDAC CONTROL/STATUS Register BADR1 + DACnR1 DACnR0 Range LSB SizeADC Fifo Clear Register BADR2 + BADR2ADC Data Register BADR2 + MSB LSBBADR3 + BADR3ADC Pacer Clock Data and Control Registers Device Counter # FunctionDIO Port a Data ADC 8254 Control RegisterDigital I/O Data and Control Registers DIO Port B DataPort a Port C Port B Upper Lower OUT DIO Port C DataDIO Control Register 8254B Counter 2 Data User Counter #6 Index and User Counter 4 Data and Control Registers8254B Counter 1 Data User Counter #5 BADR3 + Ah8254B Control Register BADR3 + BhBADR4 + BADR41 DAC0 Data Register 2 DAC1 Data RegisterElectrical Specifications Analog Output Power consumption EnvironmentalEC Declaration of Conformity