Omega Speaker Systems PCI-DAS1002, PCI-DAS1001 manual Analog Output

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8.2 ANALOG OUTPUT

D/A type

Resolution

Number of channels

Output Ranges

D/A pacing

Data transfer

Offset error

Gain error

Differential nonlinearity

Integral nonlinearity

Monotonicity

D/A Gain drift

D/A Bipolar offset drift

D/A Unipolar offset drift

Throughput

Settling time (to .01% of 10V step) Slew Rate

Current Drive

Output short-circuit duration Output Coupling

Amp Output Impedance

Miscellaneous

AD7847AR

12bits

±10V, ±5V, 0-5V, 0-10V. Each channel independently programmable.

Software

Programmed I/O.

±600µV max, all ranges (calibrated) ±0.02% FSR max (calibrated) ±1LSB max

±1LSB max 12 bits

±2 ppm/°C max ±5 ppm/°C max ±5 ppm/°C max

PC dependent 4µs typ 7V/µS

±5 mA min

25 mA indefinite

DC

0.1 Ohms max

Power up and reset, all DAC's cleared to 0 volts, ±200mV

8.3 PARAELLEL DIGITAL INPUT/OUTPUT

Digital Type	82C55A
Configuration	2 banks of 8, 2 banks of 4, programmable by bank as input or output
Number of channels	24 I/O
Output High	3.0 volts @ -2.5mA min
Output Low	0.4volts @ 2.5 mA max
Input High	2.0 volts min, Vcc+0.5 volts absolute max
Input Low	0.8 volts max, GND-0.5 volts absolute min
Power-up / reset state	Input mode (high impedance)
Interrupts	INTA# - mapped to IRQn via PCI BIOS at boot-time
Interrupt enable	Programmable
Interrupt sources	Residual counter, End-of-channel-scan, AD-FIFO-not-empty,
	AD-FIFO-half-full

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Contents Users Guide Table of Contents BADR0 BADR1 BADR2BADR3 BADR4Introduction Installation IntroductionRUN InstaCal DOS and/or WindowsConnector PIN Diagram Hardware ConnectionsAnalog Connections Single-Ended and Differential InputsSingle-Ended Inputs Differential Input Differential InputsSystem Grounds and Isolation Which system do you have?Systems with Common Mode ground offset Voltages Small Common Mode VoltagesLarge Common Mode Voltages PCI-DAS1000 and signal source already have isolated grounds Ground Category Input Configuration Our view Board Board Programming & Software Applications SELF-CALIBRATION of the PCI-DAS1000 Analog InputsAnalog Outputs BADR0 BADR1Interrupt / ADC Fifo Register Region Function OperationsInte EoaieIntcl AdflclADC Channel MUX and Control Register BADR1 + CHL8-CHL1, CHH8-CHH1EOC Pacer Source= ADC Done = ADC Busy Trigger CONTROL/STATUS Register BADR1 + TS10ARM Fifo Mode Sample CTR C0SRCXtrig IndxgtCalibration Register BADR1 +DAC Channel Cal Function Cal SourceDacen Mode DAC CONTROL/STATUS Register BADR1 +DACnR10 DACnR1 DACnR0 Range LSB SizeBADR2 ADC Data Register BADR2 +ADC Fifo Clear Register BADR2 + MSB LSBBADR3 ADC Pacer Clock Data and Control RegistersBADR3 + Device Counter # FunctionADC 8254 Control Register Digital I/O Data and Control RegistersDIO Port a Data DIO Port B DataDIO Port C Data DIO Control RegisterPort a Port C Port B Upper Lower OUT Index and User Counter 4 Data and Control Registers 8254B Counter 1 Data User Counter #58254B Counter 2 Data User Counter #6 BADR3 + Ah8254B Control Register BADR3 + BhBADR4 1 DAC0 Data RegisterBADR4 + 2 DAC1 Data RegisterElectrical Specifications Analog Output Power consumption EnvironmentalEC Declaration of Conformity