Omega Speaker Systems PCI-DAS1002, PCI-DAS1001 manual ADC Channel MUX and Control Register BADR1 +

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ADHFI Status bit of ADC FIFO Half-Full interrupt. Used during REP INSW operations. 1 = Indicates an ADC Half-Full interrupt has been latched. FIFO has been filled

with more than 255 samples.

0 = Indicates an ADC Half-Full interrupt has not occurred. FIFO has not yet exceeded 1/2 of its total capacity.

ADNEI Status bit of ADC FIFO Not-Empty interrupt. Used to indicate ADC conversion complete in single conversion applications.

1 = Indicates an ADC FIFO Not-Empty interrupt has been latched and that one data word may be read from the FIFO.

0 = Indicates an ADC FIFO Not-Empty interrupt has not occurred. FIFO has been cleared, read until empty or ADC conversion still in progress.

ADNE Real-time status bit of ADC FIFO Not-Empty status signal.

1 = Indicates ADC FIFO has at least one word to be read. 0 = Indicates ADC FIFO is empty.

LADFUL Status bit of ADC FIFO FULL status. This bit is latched.

1 = Indicates the ADC FIFO has exceeded full state. Data may have been lost. 0 = Indicates non-overflow condition of ADC FIFO.

7.3.2ADC CHANNEL MUX AND CONTROL REGISTER BADR1 + 2

This register sets channel mux HI/LO limits, ADC gain, offset and pacer source.

A Read/Write register.

WRITE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

-

ADPS1

ADPS0

UNIBIP

SEDIFF

GS1

GS0

CHH8

CHH4

CHH2

CHH1

CHL8

CHL4

CHL2

CHL1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CHL8-CHL1, CHH8-CHH1

When these bits are written, the analog input multiplexers are set to the channel specified by CHL8-CHL1. After each conversion, the input multiplexers increment to the next channel, reloading to the "CHL" start channel after the "CHH" stop channel is reached. LO and HI channels are the decode of the 4-bit binary patterns.

GS[1:0] These bits determine the ADC range as indicated below.

GS1

GS0

Range

 

 

 

0

0

10V

 

 

 

0

1

5V

 

 

 

1

0

2.5V

 

 

 

1

1

1.25V

 

 

 

 

 

 

SEDIFF Selects measurement configuration for the Analog Front-End.

1 = Analog Front-End in Single-Ended Mode. This mode supports up to 16 channels.

0 = Analog Front-End in Differential Mode. This mode supports up to 8 channels.

UNIBIP Selects offset configuration for the Analog Front-End. 1 = Analog Front-End Unipolar for selected range

0 = Analog Front-End Bipolar for selected range.

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Contents Users Guide Table of Contents BADR3 BADR0 BADR1BADR2 BADR4Introduction Installation IntroductionRUN InstaCal DOS and/or WindowsConnector PIN Diagram Hardware ConnectionsSingle-Ended and Differential Inputs Analog ConnectionsSingle-Ended Inputs Differential Input Differential InputsSystem Grounds and Isolation Which system do you have?Small Common Mode Voltages Systems with Common Mode ground offset VoltagesLarge Common Mode Voltages PCI-DAS1000 and signal source already have isolated grounds Ground Category Input Configuration Our view    Board Board Programming & Software Applications SELF-CALIBRATION of the PCI-DAS1000 Analog InputsAnalog Outputs Interrupt / ADC Fifo Register BADR0BADR1 Region Function OperationsIntcl InteEoaie AdflclADC Channel MUX and Control Register BADR1 + CHL8-CHL1, CHH8-CHH1Pacer Source EOC= ADC Done = ADC Busy TS10 Trigger CONTROL/STATUS Register BADR1 +ARM Xtrig Fifo Mode Sample CTRC0SRC IndxgtDAC Channel Cal Function Calibration RegisterBADR1 + Cal SourceDACnR10 Dacen ModeDAC CONTROL/STATUS Register BADR1 + DACnR1 DACnR0 Range LSB SizeADC Fifo Clear Register BADR2 + BADR2ADC Data Register BADR2 + MSB LSBBADR3 + BADR3ADC Pacer Clock Data and Control Registers Device Counter # FunctionDIO Port a Data ADC 8254 Control RegisterDigital I/O Data and Control Registers DIO Port B DataDIO Control Register DIO Port C DataPort a Port C Port B Upper Lower OUT 8254B Counter 2 Data User Counter #6 Index and User Counter 4 Data and Control Registers8254B Counter 1 Data User Counter #5 BADR3 + Ah8254B Control Register BADR3 + BhBADR4 + BADR41 DAC0 Data Register 2 DAC1 Data RegisterElectrical Specifications Analog Output Power consumption EnvironmentalEC Declaration of Conformity