SPI Pins and Connections
PC Parallel/SPI Port
2 3 4
For Use ONLY
with IMS Parameter
Setup Cable
15 | 19 | +5 VDC OUT |
COMM GND
7 | 9 |
P1 | 11 |
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SPI CLOCK | 8 | 12 |
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MASTER IN/SLAVE OUT MASTER OUT/SLAVE IN
CHIP SELECT
10
Figure 2.5.2: SPI Pins and Connections, 12-Pin Wire Crimp
Logic Level Shifting and Conditioning Circuit
The following circuit diagram is of a Logic Level shifting and conditioning circuit. This circuit should be used if you are making your own parameter cable and are using a laptop computer with 3.3 V output parallel ports.
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100 330pF |
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DB25: 2 | C3 |
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DB25: 3 |
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DB25: 4 |
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DB25: 19 | R5 |
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| R7 | R8 | 4.9K |
| 10 | R12 | 100K |
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DB25: 15 |
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| 6 | +5 VDC |
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NOTE: If making your own parameter setup cable, be advised the 3.3V output
parallel ports on some laptop PC’s may not be sufficient to communicate with the device without use of a logic level shifting and conditioning Interface.
Figure 2.5.3: Logic Level Shifting and Conditioning Circuit
Part 2: Interfacing and Configuring | 27 |