Cypress CY7C1141V18, CY7C1143V18 Write cycle descriptions of CY7C1145V18 follows.2, Device

Page 12

CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

The write cycle descriptions of CY7C1145V18 follows.[2, 10]

BWS

0

BWS

1

BWS

2

BWS

3

K

K

Comments

L

L

L

L

L–H

–

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

the device.

L

L

L

L

–

L–H

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

the device.

L

H

H

H

L–H

–

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

into the device. D[35:9] remains unaltered.

L

H

H

H

–

L–H

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

into the device. D[35:9] remains unaltered.

H

L

H

H

L–H

–

During the data portion of a write sequence, only the byte (D[17:9]) is written into

the device. D[8:0] and D[35:18] remains unaltered.

H

L

H

H

–

L–H

During the data portion of a write sequence, only the byte (D[17:9]) is written into

the device. D[8:0] and D[35:18] remains unaltered.

H

H

L

H

L–H

–

During the data portion of a write sequence, only the byte (D[26:18]) is written into

the device. D[17:0] and D[35:27] remains unaltered.

H

H

L

H

–

L–H

During the data portion of a write sequence, only the byte (D[26:18]) is written into

the device. D[17:0] and D[35:27] remains unaltered.

H

H

H

L

L–H

–

During the data portion of a write sequence, only the byte (D[35:27]) is written into

the device. D[26:0] remains unaltered.

H

H

H

L

–

L–H

During the data portion of a write sequence, only the byte (D[35:27]) is written into

the device. D[26:0] remains unaltered.

H

H

H

H

L–H

–

No data is written into the device during this portion of a write operation.

H

H

H

H

–

L–H

No data is written into the device during this portion of a write operation.

Document Number: 001-06583 Rev. *D

Page 12 of 28

[+] Feedback

Image 12

Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1141V18 Logic Block Diagram CY7C1156V18Logic Block Diagram CY7C1143V18 Logic Block Diagram CY7C1145V18Pin Configurations CY7C1141V18 2M xCY7C1156V18 2M x NC/144MCY7C1143V18 1M x CY7C1145V18 512K xWPS BWS WPS BWS RPSPin Definitions Pin Name Pin DescriptionBWS2, BWS3 QvldPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Read OperationsWrite Operations Byte Write OperationsValid Data Indicator Qvld Depth ExpansionProgrammable Impedance Echo ClocksApplication Example Sram #4BUS Master OperationWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle descriptions of CY7C1145V18 follows.2 DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram11TAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionIdentification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics AC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max DLL TimingSwitching Waveforms Read/Write/Deselect Sequence Waveform for 2.0 Cycle Read Latency 30, 31Diagram Ordering InformationSpeed Ordering Code Package Package Type Operating CY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI300 Package Diagram Ball Fbga 13 x 15 x 1.4 mmECN No Issue Date Orig. Description of Change Document HistoryVKN/KKVTMP VKN/AESA