Cypress CY7C1145V18 Document History, ECN No Issue Date Orig. Description of Change, Vkn/Kkvtmp

Page 28

CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

Document History Page

Document Title: CY7C1141V18/CY7C1156V18/CY7C1143V18/CY7C1145V18, 18-Mbit QDR™-II+ SRAM 4-Word Burst Archi- tecture (2.0 Cycle Read Latency)

Document Number: 001-06583

REV.

ECN No.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

**

430351

See ECN

NXR

New data sheet

 

 

 

 

 

*A

461654

See ECN

NXR

Revised the MPNs from

 

 

 

 

CY7C1156BV18 to CY7C1156V18

 

 

 

 

CY7C1143BV18 to CY7C1143V18

 

 

 

 

CY7C1145BV18 to CY7C1145V18

 

 

 

 

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH,

 

 

 

 

tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC

 

 

 

 

Switching Characteristics table

 

 

 

 

Modified Power Up waveform

*B

497629

See ECN

NXR

Changed the VDDQ operating voltage to 1.4V to VDD in the Features section, in

 

 

 

 

Operating Range table and in the DC Electrical Characteristics table

 

 

 

 

Added foot note in page 1

 

 

 

 

Changed the Maximum rating of Ambient Temperature with Power Applied from

 

 

 

 

–10°C to +85°C to –55°C to +125°C

 

 

 

 

Changed VREF (max) spec from 0.85V to 0.95V in the DC Electrical Character-

 

 

 

 

istics table and in the note below the table

 

 

 

 

Updated foot note 22 to specify Overshoot and Undershoot Spec

 

 

 

 

Updated ΘJA and ΘJC values

 

 

 

 

Removed x9 part and its related information

 

 

 

 

Updated footnote 25

*C

1167806

See ECN

VKN/KKVTMP

Converted from preliminary to final

 

 

 

 

Added x8 and x9 parts

 

 

 

 

Changed IDD values from 766 mA to 1020 mA for 375 MHz, 708 mA to 920 mA

 

 

 

 

for 333 MHz, 663 mA to 850 mA for 300 MHz

 

 

 

 

Changed ISB values from 227 mA to 290 mA for 375 MHz, 212 mA to 260 mA

 

 

 

 

for 333 MHz, 201 mA to 250 mA for 300 MHz

 

 

 

 

Changed tCYC(max) spec to 8.4 ns for all speed bins

 

 

 

 

Changed ΘJA value from 13.48 °C/W to 17.2 °C/W

 

 

 

 

Updated Ordering Information table

*D

2199066

See ECN

VKN/AESA

Added footnote# 21 related to IDD

© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-06583 Rev. *D

Revised March 06, 2008

Page 28 of 28

QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1141V18 Logic Block Diagram CY7C1156V18Logic Block Diagram CY7C1143V18 Logic Block Diagram CY7C1145V18Pin Configurations CY7C1141V18 2M xCY7C1156V18 2M x NC/144MCY7C1143V18 1M x CY7C1145V18 512K xWPS BWS WPS BWS RPSPin Definitions Pin Name Pin DescriptionBWS2, BWS3 QvldPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Read OperationsWrite Operations Byte Write OperationsValid Data Indicator Qvld Depth ExpansionProgrammable Impedance Echo ClocksApplication Example Sram #4BUS Master OperationWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle descriptions of CY7C1145V18 follows.2 DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram11TAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionScan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics AC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max DLL TimingSwitching Waveforms Read/Write/Deselect Sequence Waveform for 2.0 Cycle Read Latency 30, 31Diagram Ordering InformationSpeed Ordering Code Package Package Type Operating CY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI300 Package Diagram Ball Fbga 13 x 15 x 1.4 mmECN No Issue Date Orig. Description of Change Document HistoryVKN/KKVTMP VKN/AESA