Cypress CY7C1143V18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

Identification Register Definitions

	Instruction Field		Value			Description
	Instruction Field	CY7C1141V18	CY7C1156V18	CY7C1143V18	CY7C1145V18	Description
		CY7C1141V18	CY7C1156V18	CY7C1143V18	CY7C1145V18
	Revision Number	000	000	000	000	Version number.
	(31:29)
	Cypress Device ID	11010010101000101	11010010101001101	11010010101010101	11010010101100101	Defines the type of
	(28:12)					SRAM.
	Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Enables unique
	(11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an ID
						register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	107

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input and output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI
		and TDO. This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input and output contents. Places the boundary scan register between
		TDI and TDO. This forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input and output ring contents. Places the boundary scan register
		between TDI and TDO. This operation does not affect the SRAM operation.
RESERVED	101	Do not use: this instruction is reserved for future use.

RESERVED	110	Do not use: this instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect
		SRAM operation.

Document Number: 001-06583 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1141V18 Logic Block Diagram CY7C1156V18Logic Block Diagram CY7C1143V18 Logic Block Diagram CY7C1145V18CY7C1156V18 2M x Pin ConfigurationsCY7C1141V18 2M x NC/144MWPS BWS CY7C1143V18 1M xCY7C1145V18 512K x WPS BWS RPSBWS2, BWS3 Pin DefinitionsPin Name Pin Description QvldTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagWrite Operations Functional OverviewRead Operations Byte Write OperationsProgrammable Impedance Valid Data Indicator QvldDepth Expansion Echo ClocksBUS Master Application ExampleSram #4 OperationRemains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceInto the device. D359 remains unaltered Write cycle descriptions of CY7C1145V18 follows.2Device Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram11TAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionIdentification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in QDR-II+ SramPower Up Sequence DLL ConstraintsMaximum Ratings Electrical CharacteristicsAC Electrical Characteristics Operating RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit DLL TimingSwitching Waveforms Read/Write/Deselect Sequence Waveform for 2.0 Cycle Read Latency 30, 31Speed Ordering Code Package Package Type Operating DiagramOrdering Information CY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI300 Package Diagram Ball Fbga 13 x 15 x 1.4 mmVKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History VKN/AESA