Cypress CY7C1156V18 manual TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag

Page 7

 

 

 

 

 

 

CY7C1141V18, CY7C1156V18

 

 

 

 

 

 

 

CY7C1143V18, CY7C1145V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

 

Pin Name

IO

 

Pin Description

 

 

 

 

 

Echo Clock

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

 

 

CQ

 

 

 

 

 

 

clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”

 

 

 

 

 

 

on page 23.

 

 

 

 

 

 

 

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data

 

 

 

 

 

 

bus impedance. CQ, CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor

 

 

 

 

 

 

connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables

 

 

 

 

 

 

the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

 

 

 

 

 

 

 

 

 

 

 

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The

 

 

DOFF

 

 

 

 

 

 

timings in the DLL turned off operationis different from those listed in this data sheet. For normal

 

 

 

 

 

 

operation, connect this pin to a pull up through a 10 KΩ or less pull up resistor. The device behaves

 

 

 

 

 

 

in QDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to

 

 

 

 

 

 

167 MHz with QDR-I timing.

 

 

 

 

 

 

 

TDO

Output

TDO for JTAG.

 

 

 

 

 

 

 

TCK

Input

TCK Pin for JTAG.

 

 

 

 

 

 

 

TDI

Input

TDI Pin for JTAG.

 

 

 

 

 

 

 

TMS

Input

TMS Pin for JTAG.

 

 

 

 

 

 

 

NC

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

 

 

NC/36M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

 

 

NC/72M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

 

 

NC/144M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

 

 

NC/288M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

 

 

VREF

Input-

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and

 

 

 

 

 

Reference

AC measurement points.

 

 

VDD

Power Supply

Power Supply Inputs to the Core of the Device.

 

 

VSS

Ground

Ground for the Device.

 

 

VDDQ

Power Supply

Power Supply Inputs for the Outputs of the Device.

 

Document Number: 001-06583 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1156V18 Logic Block Diagram CY7C1141V18Logic Block Diagram CY7C1145V18 Logic Block Diagram CY7C1143V18NC/144M Pin ConfigurationsCY7C1141V18 2M x CY7C1156V18 2M xWPS BWS RPS CY7C1143V18 1M xCY7C1145V18 512K x WPS BWSQvld Pin DefinitionsPin Name Pin Description BWS2, BWS3TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagByte Write Operations Functional OverviewRead Operations Write OperationsEcho Clocks Valid Data Indicator QvldDepth Expansion Programmable ImpedanceOperation Application ExampleSram #4 BUS MasterDuring the data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredDevice. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1145V18 follows.2Device Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Tap Controller State Diagram11 TAP Controller State DiagramParameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP ControllerTAP Timing and Test Condition TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II+ SramPower Up Sequence Power Up WaveformsOperating Range Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsDLL Timing Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxWaveform for 2.0 Cycle Read Latency 30, 31 Switching Waveforms Read/Write/Deselect SequenceCY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI DiagramOrdering Information Speed Ordering Code Package Package Type Operating300 Ball Fbga 13 x 15 x 1.4 mm Package DiagramVKN/AESA ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP
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