Cypress CY7C1156V18, CY7C1145V18 manual Write Cycle Descriptions, Comments, Remains unaltered

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CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

Write Cycle Descriptions

The write cycle descriptions of CY7C1141V18 and CY7C1143V18 follows. [2, 10]

 

BWS0/

BWS1/

K

 

 

 

 

Comments

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

NWS0

 

NWS1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1141V18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1143V18 both bytes (D[17:0]) are written into the device.

 

 

 

L

 

L

 

L-H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1141V18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1143V18 both bytes (D[17:0]) are written into the device.

 

 

 

L

 

H

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1141V18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1143V18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

L

 

H

 

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1141V18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1143V18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

H

 

L

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1141V18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1143V18 only the upper byte (D[17:9]) is written into the device, D[8:0]

 

remains unaltered.

 

H

 

L

 

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1141V18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1143V18 only the upper byte (D[17:9]) is written into the device, D[8:0]

 

remains unaltered.

 

H

 

H

L–H

 

 

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

L–H

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

The write cycle descriptions of CY7C1156V18 follows.[2, 10]

 

 

 

BWS

0

 

K

 

K

 

 

 

 

Comments

 

 

 

L

 

L–H

 

 

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

 

L

 

L–H

 

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

 

H

 

L–H

 

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

H

 

L–H

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

10.Is based on a Write cycle was initiated in accordance with the Write Cycle Description Truth Table. Alter NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 on different portions of a Write cycle, as long as the setup and hold requirements are achieved.

Document Number: 001-06583 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1156V18 Logic Block Diagram CY7C1141V18Logic Block Diagram CY7C1145V18 Logic Block Diagram CY7C1143V18NC/144M Pin ConfigurationsCY7C1141V18 2M x CY7C1156V18 2M xWPS BWS RPS CY7C1143V18 1M xCY7C1145V18 512K x WPS BWSQvld Pin DefinitionsPin Name Pin Description BWS2, BWS3TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagByte Write Operations Functional OverviewRead Operations Write OperationsEcho Clocks Valid Data Indicator QvldDepth Expansion Programmable ImpedanceOperation Application ExampleSram #4 BUS MasterDuring the data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredDevice. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1145V18 follows.2Device Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Tap Controller State Diagram11 TAP Controller State DiagramParameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP ControllerTAP Timing and Test Condition TAP AC Switching CharacteristicsInstruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II+ SramPower Up Sequence Power Up WaveformsOperating Range Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsDLL Timing Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxWaveform for 2.0 Cycle Read Latency 30, 31 Switching Waveforms Read/Write/Deselect SequenceCY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI DiagramOrdering Information Speed Ordering Code Package Package Type Operating300 Ball Fbga 13 x 15 x 1.4 mm Package DiagramVKN/AESA ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP