Cypress CY7C1141V18, CY7C1156V18 manual CY7C1143V18 1M x, CY7C1145V18 512K x, Wps Bws Rps

Page 5

CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

Pin Configurations (continued)

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1143V18 (1M x 18)

 

1

 

 

 

 

2

3

4

 

 

5

 

6

 

7

 

 

8

 

 

9

10

11

A

 

 

 

 

 

 

 

NC/144M

NC/36M

 

 

 

 

 

 

 

1

 

 

 

 

 

NC/288M

 

 

 

 

 

A

NC/72M

CQ

 

 

CQ

WPS

BWS

K

RPS

B

 

 

NC

Q9

D9

 

 

A

 

NC

 

 

K

 

 

 

0

 

 

A

NC

NC

Q8

 

 

 

 

 

 

 

 

BWS

C

 

 

NC

NC

D10

 

 

VSS

 

A

NC

 

A

 

 

VSS

NC

Q7

D8

D

 

 

NC

D11

Q10

 

 

VSS

 

VSS

VSS

 

VSS

 

 

VSS

NC

NC

D7

E

 

 

NC

NC

Q11

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

D6

Q6

F

 

 

NC

Q12

D12

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

Q5

G

 

 

NC

D13

Q13

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

NC

D5

H

 

 

 

 

 

 

VREF

VDDQ

VDDQ

 

VDD

VSS

 

VDD

VDDQ

VDDQ

VREF

ZQ

 

DOFF

J

 

 

NC

NC

D14

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

Q4

D4

K

 

 

NC

NC

Q14

VDDQ

 

VDD

VSS

 

VDD

VDDQ

NC

D3

Q3

L

 

 

NC

Q15

D15

VDDQ

 

VSS

VSS

 

VSS

VDDQ

NC

NC

Q2

M

 

 

NC

NC

D16

 

 

VSS

 

VSS

VSS

 

VSS

 

 

VSS

NC

Q1

D2

N

 

 

NC

D17

Q16

 

 

VSS

 

A

 

 

A

 

A

 

 

VSS

NC

NC

D1

P

 

 

NC

NC

Q17

 

 

A

 

A

QVLD

 

A

 

 

A

NC

D0

Q0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

TDO

TCK

A

 

 

A

 

A

NC

 

A

 

 

A

A

TMS

TDI

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1145V18 (512K x 36)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

2

3

4

 

 

5

 

6

 

7

 

 

8

 

 

9

10

11

A

 

 

 

 

 

NC/288M

NC/72M

 

 

 

 

 

2

 

 

 

 

 

1

 

 

 

NC/36M

NC/144M

CQ

 

 

CQ

WPS

 

BWS

K

BWS

RPS

B

 

Q27

Q18

D18

 

 

A

 

 

3

 

 

K

 

 

 

 

A

D17

Q17

Q8

 

 

 

 

BWS

 

 

 

BWS

0

 

 

C

 

D27

Q28

D19

 

 

VSS

 

A

NC

 

A

 

 

VSS

D16

Q7

D8

D

 

D28

D20

Q19

 

 

VSS

 

VSS

VSS

 

VSS

 

 

VSS

Q16

D15

D7

E

 

Q29

D29

Q20

VDDQ

 

VSS

VSS

 

VSS

VDDQ

Q15

D6

Q6

F

 

Q30

Q21

D21

VDDQ

 

VDD

VSS

 

VDD

VDDQ

D14

Q14

Q5

G

 

D30

D22

Q22

VDDQ

 

VDD

VSS

 

VDD

VDDQ

Q13

D13

D5

H

 

 

 

VREF

VDDQ

VDDQ

 

VDD

VSS

 

VDD

VDDQ

VDDQ

VREF

ZQ

 

DOFF

 

 

J

 

D31

Q31

D23

VDDQ

 

VDD

VSS

 

VDD

VDDQ

D12

Q4

D4

K

 

Q32

D32

Q23

VDDQ

 

VDD

VSS

 

VDD

VDDQ

Q12

D3

Q3

L

 

Q33

Q24

D24

VDDQ

 

VSS

VSS

 

VSS

VDDQ

D11

Q11

Q2

M

 

D33

Q34

D25

 

 

VSS

 

VSS

VSS

 

VSS

 

 

VSS

D10

Q1

D2

N

 

D34

D26

Q25

 

 

VSS

 

A

 

 

A

 

A

 

 

VSS

Q10

D9

D1

P

 

Q35

D35

Q26

 

 

A

 

A

QVLD

 

A

 

 

A

Q9

D0

Q0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

TDO

TCK

A

 

 

A

 

A

NC

 

A

 

 

A

A

TMS

TDI

Document Number: 001-06583 Rev. *D

Page 5 of 28

[+] Feedback

Image 5
Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1156V18 Logic Block Diagram CY7C1141V18Logic Block Diagram CY7C1145V18 Logic Block Diagram CY7C1143V18CY7C1141V18 2M x Pin ConfigurationsCY7C1156V18 2M x NC/144MCY7C1145V18 512K x CY7C1143V18 1M xWPS BWS WPS BWS RPSPin Name Pin Description Pin DefinitionsBWS2, BWS3 QvldPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsDepth Expansion Valid Data Indicator QvldProgrammable Impedance Echo ClocksSram #4 Application ExampleBUS Master OperationComments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequenceDevice Write cycle descriptions of CY7C1145V18 follows.2Into the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Tap Controller State Diagram11 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max UnitTAP Timing and Test Condition TAP AC Switching CharacteristicsInstruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in QDR-II+ SramPower Up Waveforms DLL ConstraintsAC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingWaveform for 2.0 Cycle Read Latency 30, 31 Switching Waveforms Read/Write/Deselect SequenceOrdering Information DiagramSpeed Ordering Code Package Package Type Operating CY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI300 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History ECN No Issue Date Orig. Description of ChangeVKN/KKVTMP VKN/AESA