Cypress CY7C1143V18, CY7C1145V18, CY7C1141V18, CY7C1156V18 manual Idcode

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CY7C1141V18, CY7C1156V18 CY7C1143V18, CY7C1145V18

IDCODE

The IDCODE instruction causes a vendor-specific 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is supplied a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is supplied during the Update IR state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruc- tion register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in tran- sition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeat- able results may not be possible.

To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, shift the preloaded data in.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit number 47. When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition.

Set this bit by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document Number: 001-06583 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1141V18 Logic Block Diagram CY7C1156V18Logic Block Diagram CY7C1143V18 Logic Block Diagram CY7C1145V18CY7C1156V18 2M x Pin ConfigurationsCY7C1141V18 2M x NC/144MWPS BWS CY7C1143V18 1M xCY7C1145V18 512K x WPS BWS RPSBWS2, BWS3 Pin DefinitionsPin Name Pin Description QvldTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagWrite Operations Functional OverviewRead Operations Byte Write OperationsProgrammable Impedance Valid Data Indicator QvldDepth Expansion Echo ClocksBUS Master Application ExampleSram #4 OperationRemains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceInto the device. D359 remains unaltered Write cycle descriptions of CY7C1145V18 follows.2Device Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram11TAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionInstruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in QDR-II+ SramPower Up Sequence DLL ConstraintsMaximum Ratings Electrical CharacteristicsAC Electrical Characteristics Operating RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit DLL TimingSwitching Waveforms Read/Write/Deselect Sequence Waveform for 2.0 Cycle Read Latency 30, 31Speed Ordering Code Package Package Type Operating DiagramOrdering Information CY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI300 Package Diagram Ball Fbga 13 x 15 x 1.4 mmVKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History VKN/AESA
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