Cypress CY7C1156V18, CY7C1145V18, CY7C1141V18 manual Package Diagram, Ball Fbga 13 x 15 x 1.4 mm

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CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

Package Diagram

Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180

15.00±0.10

TOP VIEW

PIN 1 CORNER

15.00±0.10

BOTTOM VIEW

							PIN 1 CORNER
					Ø0.05 M C
						Ø0.25 M C A B
					Ø0.50		-0.06	(165X)
							+0.14
11	10	9	8	7	6	5	4	3	2	1
										A
										B
1.00										C
1.00										D
										D
										E
										F
14.00										G
14.00										H
										J
										K
7.00										L
7.00										M
										M
										N
										P
										R

1.00

5.00

10.00

0.25 C

	B
0.53±0.05
0.36	C
0.36

13.00±0.10

		1.40MAX.

				0.15C

SEATING PLANE

0.35±0.06

B 13.00±0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC

51-85180-*A

Document Number: 001-06583 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1156V18 Logic Block Diagram CY7C1141V18Logic Block Diagram CY7C1145V18 Logic Block Diagram CY7C1143V18NC/144M Pin ConfigurationsCY7C1141V18 2M x CY7C1156V18 2M xWPS BWS RPS CY7C1143V18 1M xCY7C1145V18 512K x WPS BWSQvld Pin DefinitionsPin Name Pin Description BWS2, BWS3TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagByte Write Operations Functional OverviewRead Operations Write OperationsEcho Clocks Valid Data Indicator QvldDepth Expansion Programmable ImpedanceOperation Application ExampleSram #4 BUS MasterDuring the data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredDevice. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1145V18 follows.2Device Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Tap Controller State Diagram11 TAP Controller State DiagramParameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP ControllerTAP Timing and Test Condition TAP AC Switching CharacteristicsIdentification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II+ SramPower Up Sequence Power Up WaveformsOperating Range Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsDLL Timing Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxWaveform for 2.0 Cycle Read Latency 30, 31 Switching Waveforms Read/Write/Deselect SequenceCY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI DiagramOrdering Information Speed Ordering Code Package Package Type Operating300 Ball Fbga 13 x 15 x 1.4 mm Package DiagramVKN/AESA ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP