Cypress CY7C1145V18 manual Power Up Sequence in QDR-II+ Sram, DLL Constraints, Power Up Waveforms

CY7C1141V18, CY7C1156V18 CY7C1143V18, CY7C1145V18

Power Up Sequence in QDR-II+ SRAM

During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock. QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

Power Up Sequence

■Apply power with DOFF tied HIGH (all other inputs can be HIGH or LOW)

❐Apply VDD before VDDQ

❐Apply VDDQ before VREF or at the same time as VREF

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency.

■Provide stable power and clock (K, K) for 2048 cycles to lock the DLL

Power Up Waveforms

Figure 5. Power Up Waveforms

K

K

VDD/VDDQ

DOFF

~ ~

	~ ~
Unstable Clock	> 2048 Stable Clock	Start Normal
Clock Start (Clock Starts after VDD/VDDQ is Stable)		Operation

VDD/VDDQ Stable (< + 0.1V DC per 50 ns)

Fix HIGH (tie to VDDQ)

Document Number: 001-06583 Rev. *D Page 20 of 28

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