Cypress CY7C1157V18 Write cycle descriptions of CY7C1148V18 follows, 3, Written into the device

Page 11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1146V18, CY7C1157V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1148V18, CY7C1150V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The write cycle descriptions of CY7C1148V18 follows, [3, 9]

 

BWS

0

 

BWS

1

 

BWS

2

 

BWS

3

K

 

K

 

Comments

 

L

 

L

 

L

 

L

L – H

 

–

When the Data portion of a write sequence is active, all four bytes (D[35:0]) are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

written into the device.

 

L

 

L

 

L

 

L

–

L – H

When the Data portion of a write sequence is active, all four bytes (D[35:0]) are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

written into the device.

 

L

 

H

 

H

 

H

L – H

 

–

When the Data portion of a write sequence is active, only the lower byte (D[8:0]) is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

written into the device. D[35:9] remains unaltered.

 

L

 

H

 

H

 

H

–

L – H

When the Data portion of a write sequence is active, only the lower byte (D[8:0]) is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

written into the device. D[35:9] remains unaltered.

 

H

 

L

 

H

 

H

L – H

 

–

When the Data portion of a write sequence is active, only the byte (D[17:9]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

L

 

H

 

H

–

L – H

When the Data portion of a write sequence is active, only the byte (D[17:9]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

H

 

L

 

H

L – H

 

–

When the Data portion of a write sequence is active, only the byte (D[26:18]) is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

written into the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

L

 

H

–

L – H

When the Data portion of a Write sequence is active, only the byte (D[26:18]) is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

written into the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

H

 

L

L – H

 

–

When the Data portion of a write sequence is active, only the byte (D[35:27]) is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

written into the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

L

–

L – H

When the Data portion of a write sequence is active, only the byte (D[35:27]) is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

written into the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

H

L – H

 

–

No data is written into the device when this portion of a write operation is active.

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

H

 

H

–

L – H

No data is written into the device when this portion of a write operation is active.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document Number: 001-06621 Rev. *D

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Contents Description 375 MHz 333 MHz 300 MHz Unit FeaturesConfigurations Selection Guide Functional DescriptionLogic Block Diagram CY7C1157V18 Logic Block Diagram CY7C1146V18Logic Block Diagram CY7C1150V18 Logic Block Diagram CY7C1148V18TMS Pin ConfigurationsCY7C1146V18 2M x CY7C1157V18 2M xTMS TDI CY7C1148V18 1M xCY7C1150V18 512K x BWSNegative Input Clock Input Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. WhenTCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Operation Truth TableSRAM#1 SRAM#2 MasterRemains unaltered When the Data portion of a write sequence is activeWrite Cycle Descriptions CommentsInto the device. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1148V18 follows, 3Written into the device Written into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State DiagramParameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP ControllerTAP Timing and Test Condition TAP AC Switching CharacteristicsInstruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II+ SramPower Up Sequence Power Up WaveformsAC Input Requirements Electrical CharacteristicsMaximum Ratings Operating RangeParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsDLL Timing Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxRead NOP Write Switching WaveformsRead/Write/Deselect Sequence NOPOrdering Information 300 Ball Fbga 13 x 15 x 1.4 mm Package DiagramVKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History NXR
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