Cypress CY7C1146V18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Identification Register Definitions

	Instruction Field		Value			Description
	Instruction Field	CY7C1146V18	CY7C1157V18	CY7C1148V18	CY7C1150V18	Description
		CY7C1146V18	CY7C1157V18	CY7C1148V18	CY7C1150V18
	Revision Number	000	000	000	000	Version number.
	(31:29)
	Cypress Device ID	11010111100000101	11010111100001101	11010111100010101	11010111100100101	Defines the type of
	(28:12)					SRAM.
	Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Allows unique
	(11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an ID
						register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	107

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the Input Output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI
		and TDO. This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the Input Output contents. Places the boundary scan register between TDI
		and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the Input Output ring contents. Places the boundary scan register between
		TDI and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect
		SRAM operation.

Document Number: 001-06621 Rev. *D

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Contents Configurations FeaturesSelection Guide Functional Description Description 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1157V18 Logic Block Diagram CY7C1146V18Logic Block Diagram CY7C1150V18 Logic Block Diagram CY7C1148V18CY7C1146V18 2M x Pin ConfigurationsCY7C1157V18 2M x TMSCY7C1150V18 512K x CY7C1148V18 1M xBWS TMS TDIPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview SRAM#1 SRAM#2 Truth TableMaster OperationWrite Cycle Descriptions When the Data portion of a write sequence is activeComments Remains unalteredWritten into the device Write cycle descriptions of CY7C1148V18 follows, 3Written into the device. D359 remains unaltered Into the device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max UnitTAP Timing and Test Condition TAP AC Switching CharacteristicsInstruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II+ SramPower Up Waveforms DLL ConstraintsMaximum Ratings Electrical CharacteristicsOperating Range AC Input RequirementsThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingRead/Write/Deselect Sequence Switching WaveformsNOP Read NOP WriteOrdering Information 300 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History ECN No Issue Date Orig. Description of ChangeNXR VKN/KKVTMP