Cypress CY7C1150V18, CY7C1148V18, CY7C1146V18, CY7C1157V18 manual Boundary Scan Order, Bit # Bump ID

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CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Boundary Scan Order

Bit #	Bump ID	Bit #	Bump ID	Bit #	Bump ID	Bit #	Bump ID
0	6R	27	11H	54	7B	81	3G

1	6P	28	10G	55	6B	82	2G

2	6N	29	9G	56	6A	83	1J

3	7P	30	11F	57	5B	84	2J

4	7N	31	11G	58	5A	85	3K

5	7R	32	9F	59	4A	86	3J

6	8R	33	10F	60	5C	87	2K

7	8P	34	11E	61	4B	88	1K

8	9R	35	10E	62	3A	89	2L

9	11P	36	10D	63	1H	90	3L

10	10P	37	9E	64	1A	91	1M

11	10N	38	10C	65	2B	92	1L

12	9P	39	11D	66	3B	93	3N

13	10M	40	9C	67	1C	94	3M

14	11N	41	9D	68	1B	95	1N

15	9M	42	11B	69	3D	96	2M

16	9N	43	11C	70	3C	97	3P

17	11L	44	9B	71	1D	98	2N

18	11M	45	10B	72	2C	99	2P

19	9L	46	11A	73	3E	100	1P

20	10L	47	Internal	74	2D	101	3R

21	11K	48	9A	75	2E	102	4R

22	10K	49	8B	76	1E	103	4P

23	9J	50	7C	77	2F	104	5P

24	9K	51	6C	78	3F	105	5N

25	10J	52	8A	79	1G	106	5R

26	11J	53	7A	80	1F

Document Number: 001-06621 Rev. *D

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Contents Selection Guide Functional Description FeaturesConfigurations Description 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1146V18 Logic Block Diagram CY7C1157V18Logic Block Diagram CY7C1148V18 Logic Block Diagram CY7C1150V18CY7C1157V18 2M x Pin ConfigurationsCY7C1146V18 2M x TMSBWS CY7C1148V18 1M xCY7C1150V18 512K x TMS TDISynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Negative Input Clock InputTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Master Truth TableSRAM#1 SRAM#2 OperationComments When the Data portion of a write sequence is activeWrite Cycle Descriptions Remains unalteredWritten into the device. D359 remains unaltered Write cycle descriptions of CY7C1148V18 follows, 3Written into the device Into the device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Shows the tap controller state diagramTAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionIdentification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsOperating Range Electrical CharacteristicsMaximum Ratings AC Input RequirementsAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit DLL TimingNOP Switching WaveformsRead/Write/Deselect Sequence Read NOP WriteOrdering Information 300 Package Diagram Ball Fbga 13 x 15 x 1.4 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP