Cypress CY7C1148V18, CY7C1146V18 TAP AC Switching Characteristics, TAP Timing and Test Condition

CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

TAP AC Switching Characteristics

The Tap AC Switching Characteristics table over the operating range follows. [14, 15]

Parameter	Description	Min	Max	Unit
tTCYC	TCK Clock Cycle Time	50		ns
tTF	TCK Clock Frequency		20	MHz
tTH	TCK Clock HIGH	20		ns
tTL	TCK Clock LOW	20		ns
Setup Times
tTMSS	TMS Setup to TCK Clock Rise	5		ns
tTDIS	TDI Setup to TCK Clock Rise	5		ns
tCS	Capture Setup to TCK Rise	5		ns
Hold Times
tTMSH	TMS Hold after TCK Clock Rise	5		ns
tTDIH	TDI Hold after Clock Rise	5		ns
tCH	Capture Hold after Clock Rise	5		ns
Output Times
tTDOV	TCK Clock LOW to TDO Valid		10	ns
tTDOX	TCK Clock LOW to TDO Invalid	0		ns

TAP Timing and Test Condition

The Tap Timing and Test Conditions for the CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 follows. [15]

Figure 4. TAP Timing and Test Conditions

			0.9V
				50Ω
TDO
	Z0	= 50Ω		CL = 20 pF

(a)GND

Test Clock

TCK

Test Mode Select

TMS

Test Data In

TDI

Test Data Out

TDO

0V

tTH

tTMSS

tTDIS

ALL INPUT PULSES

1.8V

0.9V

tTL

tTCYC

tTMSH

tTDIH

tTDOV	t
	TDOX

Notes

14.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

15.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns

Document Number: 001-06621 Rev. *D Page 16 of 27

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