Cypress CY7C1150V18, CY7C1148V18 manual Switching Characteristics, Parameter Min Max, DLL Timing

Page 22

CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Switching Characteristics

Over the operating range [21, 22]

 

Cypress

Consortium

 

 

 

 

 

 

 

 

 

 

 

 

 

Description

375 MHz

333 MHz

300 MHz

Unit

Parameter

Parameter

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

Max

Min

Max

Min

Max

tPOWER

 

 

 

VDD(Typical) to the first Access[23]

1

1

1

ms

tCYC

tKHKH

K Clock Cycle Time

2.66

8.40

3.0

8.40

3.3

8.40

ns

tKH

tKHKL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

Input Clock (K/K)

 

HIGH

0.425

0.425

0.425

tKL

tKLKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

Input Clock (K/K)

 

LOW

0.425

0.425

0.425

tKHKH

tKHKH

K Clock Rise to

 

 

 

Clock Rise (rising edge to rising edge)

1.13

1.28

1.40

ns

K

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

tAVKH

Address Setup to K Clock Rise

0.4

0.4

0.4

ns

tSC

tIVKH

Control Setup to K Clock Rise

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(LD,

R/W)

 

 

 

 

 

 

 

 

 

0.4

0.4

0.4

ns

tSCDDR

tIVKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.28

0.28

0.28

ns

Double Data Rate Control Setup to Clock (K/K)

 

Rise (BWS0,

 

 

 

 

 

 

 

BWS1, BWS2, BWS3)

 

 

 

 

 

 

 

tSD

tDVKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D[X:0] Setup to Clock (K/K)

 

 

 

Rise

0.28

0.28

0.28

ns

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHA

tKHAX

Address Hold after K Clock Rise

0.4

0.4

0.4

ns

tHC

tKHIX

Control Hold after K Clock Rise

 

 

 

 

 

 

 

 

 

 

 

0.4

0.4

0.4

ns

(LD,

R/W)

tHCDDR

tKHIX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise

 

0,

0.28

0.28

0.28

ns

Double Data Rate Control Hold after Clock (K/K)

(BWS

 

 

 

 

 

 

 

BWS1, BWS2, BWS3)

 

 

 

 

 

 

 

tHD

tKHDX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise

0.28

0.28

0.28

ns

D[X:0] Hold after Clock (K/K)

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCO

tCHQV

K/K

Clock Rise to Data Valid

0.45

0.45

0.45

ns

tDOH

tCHQX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Rise (Active to Active)

–0.45

–0.45

–0.45

ns

Data Output Hold after K/K

tCCQO

tCHCQV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K/K

Clock Rise to Echo Clock Valid

0.45

0.45

0.45

ns

tCQOH

tCHCQX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Rise

–0.45

–0.45

–0.45

ns

Echo Clock Hold after K/K

tCQD

tCQHQV

Echo Clock High to Data Valid

0.2

0.2

0.2

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.2

–0.2

–0.2

ns

tCQH

tCQHCQL

 

 

 

 

 

 

 

 

 

 

 

 

 

HIGH[24]

 

 

 

 

 

 

 

Output Clock (CQ/CQ)

0.88

1.03

1.15

ns

t

 

 

 

t

 

 

CQ Clock Rise to

 

 

Clock Rise[24]

0.88

1.03

1.15

ns

 

 

 

 

 

CQ

CQHCQH

 

 

CQHCQH

(rising edge to rising edge)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCHZ

tCHQZ

 

 

 

 

Rise to High-Z (Active to High-Z)[25, 26]

 

 

 

 

 

 

 

Clock (K/K)

0.45

0.45

0.45

ns

tCLZ

tCHQX1

 

 

 

 

Rise to Low-Z[25, 26]

 

 

 

 

 

 

 

Clock (K/K)

–0.45

–0.45

–0.45

ns

tQVLD

tQVLD

Echo Clock High to QVLD Valid[27]

–0.20

0.20

–0.20

0.20

–0.20

0.20

ns

DLL Timing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKC Var

tKC Var

Clock Phase Jitter

0.20

0.20

0.20

ns

tKC lock

tKC lock

DLL Lock Time (K)

2048

2048

2048

Cycles

tKC Reset

tKC Reset

K Static to DLL Reset[28]

30

30

30

ns

Notes

22.When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.

23.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated.

24.These parameters are extrapolated from the input timing parameters (tKHKH – 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production.

25.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

26.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

27.tQVLD spec is applicable for both rising and falling edges of QVLD signal.

28.Hold to >VIH or <VIL.

Document Number: 001-06621 Rev. *D

Page 22 of 27

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Contents Selection Guide Functional Description FeaturesConfigurations Description 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1146V18 Logic Block Diagram CY7C1157V18Logic Block Diagram CY7C1148V18 Logic Block Diagram CY7C1150V18CY7C1157V18 2M x Pin ConfigurationsCY7C1146V18 2M x TMSBWS CY7C1148V18 1M xCY7C1150V18 512K x TMS TDISynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Negative Input Clock InputTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Master Truth TableSRAM#1 SRAM#2 OperationComments When the Data portion of a write sequence is activeWrite Cycle Descriptions Remains unalteredWritten into the device. D359 remains unaltered Write cycle descriptions of CY7C1148V18 follows, 3Written into the device Into the device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Shows the tap controller state diagramTAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionScan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsOperating Range Electrical CharacteristicsMaximum Ratings AC Input RequirementsAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit DLL TimingNOP Switching WaveformsRead/Write/Deselect Sequence Read NOP WriteOrdering Information 300 Package Diagram Ball Fbga 13 x 15 x 1.4 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP