Cypress CY7C1146V18, CY7C1157V18 manual CY7C1148V18 1M x, CY7C1150V18 512K x, Bws, Tms Tdi

Page 5

CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Pin Configurations (continued)

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1148V18 (1M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

NC/144M

A

NC/36M

CQ

CQ

R/W

BWS

1

K

LD

B

NC

DQ9

NC

A

NC/288M

K

0

A

NC

NC

DQ8

BWS

C

NC

NC

NC

VSS

A

NC

A

VSS

NC

DQ7

NC

D

NC

NC

DQ10

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ11

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ6

F

NC

DQ12

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

NC

DQ13

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ4

NC

K

NC

NC

DQ14

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ3

L

NC

DQ15

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

DQ1

NC

N

NC

NC

DQ16

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ17

A

A

QVLD

A

A

NC

NC

DQ0

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

CY7C1150V18 (512K x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/144M

NC/36M

A

NC/72M

CQ

K

CQ

R/W

BWS

2

BWS1

LD

B

NC

DQ27

DQ18

A

3

K

0

A

NC

NC

DQ8

BWS

BWS

C

NC

NC

DQ28

VSS

A

NC

A

VSS

NC

DQ17

DQ7

D

NC

DQ29

DQ19

VSS

VSS

VSS

VSS

VSS

NC

NC

DQ16

E

NC

NC

DQ20

VDDQ

VSS

VSS

VSS

VDDQ

NC

DQ15

DQ6

F

NC

DQ30

DQ21

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

DQ31

DQ22

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ14

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

DQ32

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ13

DQ4

K

NC

NC

DQ23

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ12

DQ3

L

NC

DQ33

DQ24

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

DQ34

VSS

VSS

VSS

VSS

VSS

NC

DQ11

DQ1

N

NC

DQ35

DQ25

VSS

A

A

A

VSS

NC

NC

DQ10

P

NC

NC

DQ26

A

A

QVLD

A

A

NC

DQ9

DQ0

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

Document Number: 001-06621 Rev. *D

Page 5 of 27

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Contents Configurations FeaturesSelection Guide Functional Description Description 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1157V18 Logic Block Diagram CY7C1146V18Logic Block Diagram CY7C1150V18 Logic Block Diagram CY7C1148V18CY7C1146V18 2M x Pin ConfigurationsCY7C1157V18 2M x TMSCY7C1150V18 512K x CY7C1148V18 1M xBWS TMS TDIPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview SRAM#1 SRAM#2 Truth TableMaster OperationWrite Cycle Descriptions When the Data portion of a write sequence is activeComments Remains unalteredWritten into the device Write cycle descriptions of CY7C1148V18 follows, 3Written into the device. D359 remains unaltered Into the device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max UnitTAP Timing and Test Condition TAP AC Switching CharacteristicsInstruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II+ SramPower Up Waveforms DLL ConstraintsMaximum Ratings Electrical CharacteristicsOperating Range AC Input RequirementsThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingRead/Write/Deselect Sequence Switching WaveformsNOP Read NOP WriteOrdering Information 300 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History ECN No Issue Date Orig. Description of ChangeNXR VKN/KKVTMP