Cypress CY7C1150V18, CY7C1148V18 manual Write Cycle Descriptions, Comments, Remains unaltered

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CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Write Cycle Descriptions

The write cycle descriptions of CY7C1146V18 and CY7C1148V18 follows. [3, 9]

 

BWS0/

BWS1/

K

 

 

 

Comments

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

NWS0

 

NWS1

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

L – H

 

When the Data portion of a write sequence is active:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1146V18 − both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1148V18 − both bytes (D[17:0]) are written into the device.

 

 

 

L

 

L

L – H

When the Data portion of a write sequence is active:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1146V18 − both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1148V18 − both bytes (D[17:0]) are written into the device.

 

 

 

L

 

H

L – H

 

When the Data portion of a write sequence is active:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1146V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1148V18 − only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

L

 

H

L – H

When the Data portion of a write sequence is active:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1146V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1148V18 − only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

H

 

L

L – H

 

When the Data portion of a write sequence is active:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1146V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1148V18 − only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

H

 

L

L – H

When the Data portion of a write sequence is active:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1146V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1148V18 − only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

H

 

H

L – H

 

No data is written into the devices when this portion of a write operation is active.

 

 

 

 

 

 

 

 

H

 

H

L – H

No data is written into the devices when this portion of a write operation is active.

 

 

 

 

 

 

 

 

 

 

 

 

 

The write cycle descriptions of CY7C1146V18 follows. [3, 9]

 

BWS0

K

 

K

Comments

 

L

L – H

 

When the Data portion of a write sequence is active, the single byte (D[8:0]) is written into the device.

 

L

L – H

When the Data portion of a write sequence is active, the single byte (D[8:0]) is written into the device.

 

H

L – H

 

No data is written into the device when this portion of a write operation is active.

 

 

 

 

 

 

H

L – H

No data is written into the device when this portion of a write operation is active.

 

 

 

 

 

 

 

 

Note

9.Is based on a Write cycle was initiated in accordance with the Write Cycle Description Truth Table. Alter BWS0, BWS1, BWS2, and BWS3 on different portions of a Write cycle, as long as the setup and hold requirements are achieved.

Document Number: 001-06621 Rev. *D

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Contents Selection Guide Functional Description FeaturesConfigurations Description 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1146V18 Logic Block Diagram CY7C1157V18Logic Block Diagram CY7C1148V18 Logic Block Diagram CY7C1150V18CY7C1157V18 2M x Pin ConfigurationsCY7C1146V18 2M x TMSBWS CY7C1148V18 1M xCY7C1150V18 512K x TMS TDISynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Negative Input Clock InputTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Master Truth TableSRAM#1 SRAM#2 OperationComments When the Data portion of a write sequence is activeWrite Cycle Descriptions Remains unalteredWritten into the device. D359 remains unaltered Write cycle descriptions of CY7C1148V18 follows, 3Written into the device Into the device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Shows the tap controller state diagramTAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionScan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsOperating Range Electrical CharacteristicsMaximum Ratings AC Input RequirementsAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit DLL TimingNOP Switching WaveformsRead/Write/Deselect Sequence Read NOP WriteOrdering Information 300 Package Diagram Ball Fbga 13 x 15 x 1.4 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP