Cypress CY7C1146V18, CY7C1148V18, CY7C1150V18 manual Truth Table, SRAM#1 SRAM#2, Master, Operation

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CY7C1146V18, CY7C1157V18 CY7C1148V18, CY7C1150V18

echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives.

DLL

These chips utilize a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in

DDR-I mode (with 1.0 cycle latency and a longer access time). For more information, refer to the application note, “DLL Consid- erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be reset in order to lock to the desired frequency. During Power up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock.

Application Example

Figure 1 shows two DDR-II+ used in an application.

Figure 1. Application Example

 

 

 

SRAM#1

 

ZQ

 

 

SRAM#2

 

ZQ

 

 

 

DQ

CQ/CQ

R = 250ohms

DQ

CQ/CQ

R = 250ohms

 

 

 

 

 

 

 

 

A

LD

R/W

K

K

 

A

LD

R/W

K

K

 

 

 

DQ

 

 

 

 

 

 

 

 

 

 

 

BUS

 

Addresses

 

 

 

 

 

 

 

 

 

 

 

MASTER

Cycle Start

 

 

 

 

 

 

 

 

 

 

 

(CPU or ASIC)

R/W

 

 

 

 

 

 

 

 

 

 

 

 

Source CLK

 

 

 

 

 

 

 

 

 

 

 

 

Source CLK

 

 

 

 

 

 

 

 

 

 

 

Echo Clock1/Echo Clock1

 

 

 

 

 

 

 

 

 

 

 

Echo Clock2/Echo Clock2

 

 

 

 

 

 

 

 

 

 

 

Truth Table

The truth table for the CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 follows. [3, 4, 5, 6, 7, 8]

Operation

K

 

LD

R/W

DQ

DQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle:

L – H

 

L

L

D(A) at K (t + 1) ↑

D(A + 1) at

 

 

 

(t + 1) ↑

K

Load address; wait one cycle; input write data on consecutive

 

 

 

 

 

 

 

 

 

 

 

 

 

K and K rising edges.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle: (2.0 cycle latency)

L – H

 

L

H

Q(A) at K (t + 2)↑

Q(A + 1) at

 

 

(t + 2) ↑

K

Load address; wait two cycle; read data on consecutive K and

 

 

 

 

 

 

 

 

 

 

 

 

 

K rising edges.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP: No Operation

L – H

 

H

X

High-Z

High-Z

 

 

 

 

 

 

 

Standby: Clock Stopped

Stopped

 

X

X

Previous State

Previous State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

2.The above application shows two DDR-II+ used.

3.X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.

4.Device powers up deselected and the outputs in a tri-state condition.

5.“A” represents address location latched by the devices when transaction was initiated and A + 1 represents the addresses sequence in the burst.

6.“t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

7.Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.

8.It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

Document Number: 001-06621 Rev. *D

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Contents Configurations FeaturesSelection Guide Functional Description Description 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1157V18 Logic Block Diagram CY7C1146V18Logic Block Diagram CY7C1150V18 Logic Block Diagram CY7C1148V18CY7C1146V18 2M x Pin ConfigurationsCY7C1157V18 2M x TMSCY7C1150V18 512K x CY7C1148V18 1M xBWS TMS TDIPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview SRAM#1 SRAM#2 Truth TableMaster OperationWrite Cycle Descriptions When the Data portion of a write sequence is activeComments Remains unalteredWritten into the device Write cycle descriptions of CY7C1148V18 follows, 3Written into the device. D359 remains unaltered Into the device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max UnitTAP Timing and Test Condition TAP AC Switching CharacteristicsIdentification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II+ SramPower Up Waveforms DLL ConstraintsMaximum Ratings Electrical CharacteristicsOperating Range AC Input RequirementsThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingRead/Write/Deselect Sequence Switching WaveformsNOP Read NOP WriteOrdering Information 300 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History ECN No Issue Date Orig. Description of ChangeNXR VKN/KKVTMP
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