Cypress CY7C1150V18 Pin Definitions, Pin Name Pin Description, Synchronous Read/Write Input. When

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CY7C1146V18, CY7C1157V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1148V18, CY7C1150V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

IO

 

 

 

 

 

 

 

Pin Description

 

 

DQ[x:0]

Input Output-

Data Input Output Signals. Inputs are sampled on the rising edge of K and

 

clocks when write

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

operations are valid. These pins drive out the requested data when a read operation is active. Valid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

data is driven out on the rising edge of both the K and K clocks when read operations are active.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When read access is deselected, Q[x:0] are automatically tri-stated.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1146V18 − DQ[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1157V18 − DQ[8:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1148V18 − DQ[17:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1150V18 − DQ[35:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. This

 

 

LD

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

definition includes address and read/write direction. All transactions operate on a burst of two data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LD must meet the setup and hold times around edge of K.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0,

 

 

 

1,

Input-

Nibble Write Select 0, 1 − Active LOW.(CY7C1146V18 Only) Sampled on the rising edge of the K

 

 

NWS

NWS

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

and K clocks when the write operation is active. It is used to select the nibble that is written into the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

device NWS0 controls D[3:0] and NWS1 controls D[7:4].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Select causes the corresponding nibble of data to be ignored and not written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0,

 

 

1,

Input-

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and

 

 

clocks

 

 

BWS

BWS

K

 

BWS2, BWS3

Synchronous

when the Write operation is active. It is used to select the byte that is written into the device when

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the current portion of the write operation is active. Bytes not written remain unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1157V18 − BWS0

controls D[8:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1148V18 − BWS0

controls D[8:0], and

BWS

1 controls D[17:9].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1148V18 − BWS0

controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18], and BWS3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

controls D[35:27].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

causes the corresponding byte of data to be ignored and not written into the device.

 

 

 

 

 

 

 

A

Input-

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

These address inputs are multiplexed for both read and write operations. Internally, the device is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

organized as 2M x 8 (two arrays each of1M x 8) for CY7C1146V18, 2M x 9 (two arrays each of 1M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x 9) for CY7C1157V18, 1M x 18 (two arrays each of 512K x 18) for CY7C1148V18, and 512K x 36

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(two arrays each of 256K x 18) for CY7C1150V18. All the address inputs are ignored when the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

appropriate port is deselected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Synchronous Read/Write Input. When

 

 

is LOW, this input designates the access type (read

 

 

R/W

LD

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

 

 

 

 

is LOW) for loaded address. R/W must meet the setup and hold

 

 

 

 

 

 

 

 

 

 

 

 

 

 

when R/W is HIGH, write when R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

times around edge of K.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QVLD

Valid Output

Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Indicator

CQ.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

Input-

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

edge of K.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Negative Input Clock Input.

 

is used to capture synchronous inputs being presented to the device

 

 

K

K

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

and to drive out data through Q[x:0] when in single clock mode.

 

 

CQ

Clock Output

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

clock (K) of the DDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

on page 22.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Output

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

 

 

CQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

clock (K) of the DDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

on page 22.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document Number: 001-06621 Rev. *D

 

 

 

 

 

 

 

 

 

 

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Contents Selection Guide Functional Description FeaturesConfigurations Description 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1146V18 Logic Block Diagram CY7C1157V18Logic Block Diagram CY7C1148V18 Logic Block Diagram CY7C1150V18CY7C1157V18 2M x Pin ConfigurationsCY7C1146V18 2M x TMSBWS CY7C1148V18 1M xCY7C1150V18 512K x TMS TDISynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Negative Input Clock InputTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Master Truth TableSRAM#1 SRAM#2 OperationComments When the Data portion of a write sequence is activeWrite Cycle Descriptions Remains unalteredWritten into the device. D359 remains unaltered Write cycle descriptions of CY7C1148V18 follows, 3Written into the device Into the device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Shows the tap controller state diagramTAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionIdentification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsOperating Range Electrical CharacteristicsMaximum Ratings AC Input RequirementsAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit DLL TimingNOP Switching WaveformsRead/Write/Deselect Sequence Read NOP WriteOrdering Information 300 Package Diagram Ball Fbga 13 x 15 x 1.4 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP
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