Cypress CY7C1148V18, CY7C1146V18, CY7C1150V18, CY7C1157V18 manual Ordering Information

Page 24

CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Ordering Information

Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
375	CY7C1146V18-375BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1157V18-375BZC

	CY7C1148V18-375BZC

	CY7C1150V18-375BZC

	CY7C1146V18-375BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1157V18-375BZXC

	CY7C1148V18-375BZXC

	CY7C1150V18-375BZXC

	CY7C1146V18-375BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1157V18-375BZI

	CY7C1148V18-375BZI

	CY7C1150V18-375BZI

	CY7C1146V18-375BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1157V18-375BZXI

	CY7C1148V18-375BZXI

	CY7C1150V18-375BZXI

333	CY7C1146V18-333BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1157V18-333BZC

	CY7C1148V18-333BZC

	CY7C1150V18-333BZC

	CY7C1146V18-333BZXC	51-85180	165-Vall Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1157V18-333BZXC

	CY7C1148V18-333BZXC

	CY7C1150V18-333BZXC

	CY7C1146V18-333BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1157V18-333BZI

	CY7C1148V18-333BZI

	CY7C1150V18-333BZI

	CY7C1146V18-333BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1157V18-333BZXI

	CY7C1148V18-333BZXI

	CY7C1150V18-333BZXI

Document Number: 001-06621 Rev. *D

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Contents Features ConfigurationsSelection Guide Functional Description Description 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1146V18 Logic Block Diagram CY7C1157V18Logic Block Diagram CY7C1148V18 Logic Block Diagram CY7C1150V18Pin Configurations CY7C1146V18 2M xCY7C1157V18 2M x TMSCY7C1148V18 1M x CY7C1150V18 512K xBWS TMS TDIPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Truth Table SRAM#1 SRAM#2Master OperationWhen the Data portion of a write sequence is active Write Cycle DescriptionsComments Remains unalteredWrite cycle descriptions of CY7C1148V18 follows, 3 Written into the deviceWritten into the device. D359 remains unaltered Into the device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Shows the tap controller state diagramTAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionIdentification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics Maximum RatingsOperating Range AC Input RequirementsCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max DLL TimingSwitching Waveforms Read/Write/Deselect SequenceNOP Read NOP WriteOrdering Information 300 Package Diagram Ball Fbga 13 x 15 x 1.4 mmECN No Issue Date Orig. Description of Change Document HistoryNXR VKN/KKVTMP