Cypress CY7C1157V18, CY7C1146V18 Logic Block Diagram CY7C1148V18, Logic Block Diagram CY7C1150V18

Page 3

CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Logic Block Diagram (CY7C1148V18)

A(18:0)

Address

CLK

Gen.

DOFF

VREF

Control

R/W

Logic

BWS

[1:0]

Write	Write
Reg	Reg

Decode	512K x	512K x
Write Add.	18 Array	18 Array
	Read Data Reg.
		36
		18
		18

Read Add. Decode

Output

Logic

R/W

Control

Reg.

DQ[17:0]

Reg.

QVLD

Logic Block Diagram (CY7C1150V18)

A(17:0)

Address

CLK

Gen.

DOFF

VREF

Control

R/W

Logic

BWS

[3:0]

Write	Write
Reg	Reg

Decode	256K x	256K x
Write Add.	36 Array	36 Array
	Read Data Reg.
		72
		36
		36

Read Add. Decode

Output

Logic

R/W

Control

Reg.

DQ[35:0]

Reg.

QVLD

Document Number: 001-06621 Rev. *D

Page 3 of 27

[+] Feedback

Image 3

Contents Description 375 MHz 333 MHz 300 MHz Unit FeaturesConfigurations Selection Guide Functional DescriptionLogic Block Diagram CY7C1157V18 Logic Block Diagram CY7C1146V18Logic Block Diagram CY7C1150V18 Logic Block Diagram CY7C1148V18TMS Pin ConfigurationsCY7C1146V18 2M x CY7C1157V18 2M xTMS TDI CY7C1148V18 1M xCY7C1150V18 512K x BWSNegative Input Clock Input Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. WhenTCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Operation Truth TableSRAM#1 SRAM#2 MasterRemains unaltered When the Data portion of a write sequence is activeWrite Cycle Descriptions CommentsInto the device. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1148V18 follows, 3Written into the device Written into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State DiagramParameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP ControllerTAP Timing and Test Condition TAP AC Switching CharacteristicsIdentification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II+ SramPower Up Sequence Power Up WaveformsAC Input Requirements Electrical CharacteristicsMaximum Ratings Operating RangeParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsDLL Timing Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxRead NOP Write Switching WaveformsRead/Write/Deselect Sequence NOPOrdering Information 300 Ball Fbga 13 x 15 x 1.4 mm Package DiagramVKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History NXR