Cypress CY7C1314BV18 manual Write cycle description table for CY7C1910BV18 follows, Device

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CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Write Cycle Descriptions

The write cycle description table for CY7C1910BV18 follows. [2, 8]

BWS0

K

K

Comments

L

L–H

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

L

L–H

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

Write Cycle Descriptions

The write cycle description table for CY7C1314BV18 follows. [2, 8]

 

BWS0

 

BWS1

 

BWS2

 

BWS3

K

 

K

Comments

 

L

 

L

 

L

 

L

L–H

 

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

L

 

L

 

L

 

L

L–H

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

L

 

H

 

H

 

H

L–H

 

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

L

 

H

 

H

 

H

L–H

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

H

 

L

 

H

 

H

L–H

 

During the data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

L

 

H

 

H

L–H

During the data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

H

 

L

 

H

L–H

 

During the data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

L

 

H

L–H

During the data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

H

 

L

L–H

 

During the data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

L

L–H

During the data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

H

L–H

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

H

 

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-05619 Rev. *F

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Contents Selection Guide FeaturesConfigurations Functional DescriptionDoff Logic Block Diagram CY7C1310BV18Logic Block Diagram CY7C1910BV18 Logic Block Diagram CY7C1314BV18 Logic Block Diagram CY7C1312BV18CY7C1910BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1310BV18 2M xNC/72M NC/36M CY7C1312BV18 1M xWPS BWS CY7C1314BV18 512K xPin Name Pin Description Pin DefinitionsTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toFunctional Overview Sram #1 Application ExampleProgrammable Impedance Echo ClocksComments Truth TableWrite Cycle Descriptions OperationInto the device. D359 remains unaltered Write cycle description table for CY7C1910BV18 followsWrite cycle description table for CY7C1314BV18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document # 38-05619 Rev. *F AC Electrical CharacteristicsInput High Voltage Vref + Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitDLL Timing Switching CharacteristicsCypress Consortium Description 250 MHz 200 MHz 167 MHz Unit Parameter Min MaxRead/Write/Deselect Sequence 26, 27 Switching WaveformsOrdering Information 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramNXR Document HistorySYT VKN/PYRS Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN